Searched refs:x10 (Results 226 - 250 of 2274) sorted by relevance

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/openbsd-current/sys/arch/arm64/arm64/
H A Dsupport.S93 stp xzr, xzr, [x0], #0x10
94 stp xzr, xzr, [x0], #0x10
95 stp xzr, xzr, [x0], #0x10
96 stp xzr, xzr, [x0], #0x10
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.h33 #define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
53 #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
/openbsd-current/sys/dev/usb/
H A Ducomvar.h66 #define ULSR_BI 0x10 /* Break detected */
78 #define UMSR_CTS 0x10 /* Current Clear to Send */
H A Dif_axenreg.h105 #define AXEN_EEPROM_BUSY 0x10
111 #define AXEN_MONITOR_RW_FLAG 0x10
119 #define AXEN_PHYCLK_ACSREQ 0x10
126 #define AXEN_RXCOE_IGMP 0x10
136 #define AXEN_TXCOE_IGMP 0x10
186 #define AXEN_CMD_MAC_NODE_ID 0x10
205 #define AXEN_GPIO2_EN 0x10
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dpolaris_baco.c75 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
76 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
78 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
79 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
159 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
160 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
162 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, 0x10, 0x4, 0, 0x1 },
163 { CMD_WAITFOR, mmGCK_SMC_IND_DATA, 0x10, 0, 1, 0 },
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h40 #define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
48 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
66 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
84 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
102 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
120 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
138 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
156 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
174 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
298 #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
[all...]
/openbsd-current/gnu/usr.bin/binutils/opcodes/
H A Darc-ext.c41 opcode = 0x1f - 0x10 + minor - 0x09 + 1;
44 if (opcode < 0x10)
47 opcode -= 0x10;
186 opcode = 0x1f - 0x10 + minor - 0x09 + 1;
188 opcode -= 0x10;
/openbsd-current/gnu/usr.bin/binutils-2.17/opcodes/
H A Darc-ext.c42 opcode = 0x1f - 0x10 + minor - 0x09 + 1;
45 if (opcode < 0x10)
48 opcode -= 0x10;
187 opcode = 0x1f - 0x10 + minor - 0x09 + 1;
189 opcode -= 0x10;
/openbsd-current/sys/dev/ic/
H A Ds3_617.h39 SV_SB_PORTBASE_SLOT = 0x10,
97 SV_DMA_MODE_AUTOINIT = 0x10
151 SV_LEFT_PCM_INPUT_CONTROL = 0x10,
196 SV_DMAC_STEREO = 0x10,
213 SV_MIC_BOOST_BIT = 0x10,
H A Dcacreg.h66 #define CAC_REG_STATUS 0x10
84 #define CAC_EISAREG_COMPLETE_ADDR 0x10
99 #define CAC_CMD_GET_LOG_DRV_INFO 0x10
119 #define CAC_RET_CMD_INVALID 0x10
202 #define CAC_LD_USED 0x10 /* at least one spare drive is used */
/openbsd-current/sys/dev/pci/
H A Dpciide_hpt_reg.h57 #define HPT366_CTRL1_CHANEN(chan) (0x10 << (chan))
64 #define HPT366_CTRL2_SGEN 0x10
79 #define HPT370_CTRL1_CLRSGC 0x10
110 #define HPT_CSEL_IRQDIS 0x10 /* 370 only */
118 #define HPT_SC2_ECLK 0x10
H A Denvyreg.h23 #define ENVY_CTL_BAR 0x10
34 #define ENVY_CCS_INT_MT 0x10
69 #define ENVY_I2C_DEV 0x10
127 #define ENVY_MT_AC97_CMD_RD 0x10
131 #define ENVY_MT_PADDR 0x10
200 #define AK4524_FMT_384 0x10
228 #define AK4358_SPEED_DFS0 0x10 /* rate multiplier (1x, 2x, 4x) */
/openbsd-current/sys/dev/wsfont/
H A Dspleen6x12.h116 0x10, /* ...*.... */
165 0x10, /* ...*.... */
172 0x10, /* ...*.... */
244 0x10, /* ...*.... */
245 0x10, /* ...*.... */
314 0x10, /* ...*.... */
315 0x10, /* ...*.... */
350 0x10, /* ...*.... */
413 0x10, /* ...*.... */
418 0x10, /*
[all...]
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_2_0_0_sh_mask.h429 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
463 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
480 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
548 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
565 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
582 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
599 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
616 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10
633 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10
1230 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
[all...]
H A Dmmhub_9_4_1_sh_mask.h366 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
400 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
417 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
485 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
502 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
519 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
536 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
1070 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
1104 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
1121 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
[all...]
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_3_sh_mask.h56 #define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10
92 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
183 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
246 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x10
291 #define SDMA0_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10
300 #define SDMA0_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10
316 #define SDMA0_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10
337 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
346 #define SDMA0_VERSION__REV__SHIFT 0x10
367 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
[all...]
H A Dgc_9_4_3_sh_mask.h52 #define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
116 #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
208 #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
294 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
395 #define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10
403 #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
407 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
433 #define GRBM_FENCE_RANGE0__END__SHIFT 0x10
438 #define GRBM_FENCE_RANGE1__END__SHIFT 0x10
492 #define CP_CPC_DEBUG_CNTL__DEBUG_BUS_SELECT_BITS__SHIFT 0x10
[all...]
H A Dgc_11_0_0_sh_mask.h56 #define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10
89 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
177 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
233 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x10
275 #define SDMA0_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10
284 #define SDMA0_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10
300 #define SDMA0_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10
319 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
328 #define SDMA0_VERSION__REV__SHIFT 0x10
349 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10
[all...]
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/hdp/
H A Dhdp_5_2_1_sh_mask.h33 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
42 #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10
151 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10
182 #define HDP_VERSION__REV__SHIFT 0x10
210 #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
248 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
262 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
481 #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
488 #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
495 #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
[all...]
H A Dhdp_5_0_0_sh_mask.h31 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
40 #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10
163 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10
203 #define HDP_VERSION__REV__SHIFT 0x10
233 #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
271 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
285 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
508 #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
515 #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
522 #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
[all...]
H A Dhdp_4_4_2_sh_mask.h33 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10
42 #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10
157 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT 0x10
197 #define HDP_VERSION__REV__SHIFT 0x10
227 #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10
265 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
279 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
508 #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
515 #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
522 #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
[all...]
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_sh_mask.h35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
58 #define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10
67 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
92 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
122 #define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10
127 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
143 #define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
168 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
191 #define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
224 #define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
[all...]
/openbsd-current/sys/dev/microcode/rum/
H A Dmicrocode.h26 0x02, 0x13, 0x25, 0x12, 0x10, 0xd9, 0x02, 0x12, 0x58, 0x02, 0x13,
41 0xfe, 0x90, 0x00, 0x10, 0x80, 0x24, 0x90, 0x00, 0x1b, 0xe0, 0x30,
65 0x12, 0x57, 0x90, 0x00, 0x11, 0xe0, 0xfe, 0x90, 0x00, 0x10, 0x80,
74 0x38, 0x13, 0xfd, 0x12, 0x10, 0x20, 0xe5, 0x3c, 0x30, 0xe2, 0x04,
79 0x90, 0x03, 0x27, 0x74, 0x02, 0xf0, 0xaf, 0x40, 0x12, 0x10, 0x74,
95 0x30, 0xe1, 0x04, 0x30, 0x0e, 0xf6, 0x22, 0x7f, 0x25, 0x12, 0x10,
111 0xe5, 0x24, 0x30, 0xe0, 0x05, 0x43, 0x05, 0x10, 0x80, 0x03, 0x53,
118 0x3f, 0xe9, 0x30, 0xe0, 0x05, 0x43, 0x05, 0x10, 0x80, 0x03, 0x53,
125 0x54, 0xc0, 0x60, 0x05, 0x43, 0x03, 0x10, 0x80, 0x03, 0x53, 0x03,
135 0xad, 0x09, 0x12, 0x13, 0xc5, 0x80, 0x10,
[all...]
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h49 #define BUS_CNTL__PMI_BM_DIS_MASK 0x10
64 #define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
102 #define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
108 #define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
124 #define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
139 #define HW_DEBUG__HW_04_DEBUG_MASK 0x10
164 #define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
198 #define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
239 #define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10
250 #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10
[all...]
/openbsd-current/sys/arch/luna88k/stand/boot/
H A Dscsireg.h48 #define SCTL_ABRT_ENAB 0x10
54 #define SCMD_RST 0x10
74 #define INTS_CMD_DONE 0x10
83 #define PSNS_SEL 0x10
91 #define SSTS_XFR 0x10
161 #define CMD_WRITE_FILEMARK 0x10
191 #define STS_INTERMED 0x10 /* Intermediate status sent */

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