1/*	$OpenBSD: if_axenreg.h,v 1.7 2024/01/04 08:41:59 kevlo Exp $	*/
2
3/*
4 * Copyright (c) 2013 Yojiro UO <yuo@openbsd.org>. All right reserved.
5 *
6 */
7
8/*
9 * Definitions for the ASIX Electronics AX88179 to ethernet controller.
10 */
11
12#define AXEN_PHY_ID		0x0003
13#define AXEN_MCAST_FILTER_SIZE	8
14/* unit: KB */
15#define AXEN_BUFSZ_LS		8
16#define AXEN_BUFSZ_HS		16
17#define AXEN_BUFSZ_SS		24
18
19#define AXEN_REV_UA1		0
20#define AXEN_REV_UA2		1
21
22/* receive header */
23/*
24 *                     +-multicast/broadcast
25 *                     |    +-rx_ok
26 *                     |    |     ++-----L3_type (1:ipv4, 0/2:ipv6)
27 *        pkt_len(13)  |    |     ||+ ++-L4_type(0: icmp, 1: UDP, 4: TCP)
28 * |765|43210 76543210|7654 3210 7654 3210|
29 *  ||+-crc_err              |+-L4_err |+-L4_CSUM_ERR
30 *  |+-mii_err               +--L3_err +--L3_CSUM_ERR
31 *  +-drop_err
32 *
33 * ex) pkt_hdr 0x00680820
34 *      drop_err, crc_err: none
35 *      pkt_length = 104 byte
36 *      0x0820 = 0000 1000 0010 0000  => ipv4 icmp
37 *
38 * ex) pkt_hdr 0x004c8800
39 *      drop_err, crc_err: none
40 *      pkt_length = 76 byte
41 *      0x8800 = 1000 1000 0000 0000 => ipv6 mcast icmp
42 *
43 *  [memo]
44 *  0x0820: ipv4 icmp			0000 1000 0010 0000
45 *  0x8820: ipv4 icmp (broadcast)	1000 1000 0010 0000
46 *  0x0824: ipv4 udp (nping)		0000 1000 0010 0100
47 *  0x0830: ipv4 tcp (ssh)		0000 1000 0011 0000
48 *
49 *  0x0800: ipv6 icmp			0000 1000 0000 0000
50 *  0x8800: ipv6 icmp (multicast)	1000 1000 0000 0000
51 *  0x8844: ipv6 UDP/MDNS mcast		1000 1000 0100 0100
52 *  0x0850: ipv6 tcp (ssh)		0000 1000 0101 0000
53 */
54
55#define	AXEN_RXHDR_DROP_ERR	(1U << 31)
56#define AXEN_RXHDR_MII_ERR	(1U << 30)
57#define	AXEN_RXHDR_CRC_ERR	(1U << 29)
58#define AXEN_RXHDR_MCAST	(1U << 15)
59#define AXEN_RXHDR_RX_OK	(1U << 11)
60#define	AXEN_RXHDR_L3_ERR	(1U << 9)
61#define	AXEN_RXHDR_L4_ERR	(1U << 8)
62#define AXEN_RXHDR_L3CSUM_ERR 	(1U << 1)
63#define AXEN_RXHDR_L4CSUM_ERR	(1U << 0)
64
65/* L4 packet type (3bit) */
66#define AXEN_RXHDR_L4_TYPE_MASK	0x0000001c
67#define AXEN_RXHDR_L4_TYPE_OFFSET	2
68#define   AXEN_RXHDR_L4_TYPE_ICMP	0x0
69#define   AXEN_RXHDR_L4_TYPE_UDP	0x1
70#define   AXEN_RXHDR_L4_TYPE_TCP	0x4
71
72/* L3 packet type (2bit) */
73#define AXEN_RXHDR_L3_TYPE_MASK	0x00000600
74#define AXEN_RXHDR_L3_TYPE_OFFSET	5
75#define   AXEN_RXHDR_L3_TYPE_UNDEF	0x0
76#define   AXEN_RXHDR_L3_TYPE_IPV4	0x1
77#define   AXEN_RXHDR_L3_TYPE_IPV6	0x2
78
79/*
80 * commands
81 */
82#define AXEN_CMD_LEN(x)	(((x) & 0xF000) >> 12)
83#define AXEN_CMD_DIR(x)	(((x) & 0x0F00) >> 8)
84#define AXEN_CMD_CMD(x)	 ((x) & 0x00FF)
85
86/* ---MAC--- */
87/*   1byte cmd   */
88#define AXEN_CMD_MAC_READ			0x1001
89#define AXEN_CMD_MAC_WRITE			0x1101
90
91#define   AXEN_USB_UPLINK			0x02
92#define     AXEN_USB_FS				  0x01
93#define     AXEN_USB_HS				  0x02
94#define     AXEN_USB_SS				  0x04
95#define   AXEN_GENERAL_STATUS			0x03
96#define     AXEN_GENERAL_STATUS_MASK		  0x4
97#define     AXEN_REV0				  0x0
98#define     AXEN_REV1				  0x4
99#define   AXEN_UNK_05				0x05
100#define   AXEN_MAC_EEPROM_ADDR			0x07
101#define   AXEN_MAC_EEPROM_READ			0x08
102#define   AXEN_MAC_EEPROM_CMD			0x0a
103#define     AXEN_EEPROM_READ			  0x04
104#define     AXEN_EEPROM_WRITE			  0x08
105#define     AXEN_EEPROM_BUSY			  0x10
106#define   AXEN_MONITOR_MODE			0x24
107#define     AXEN_MONITOR_NONE			  0x00
108#define     AXEN_MONITOR_RWLC			  0x02
109#define     AXEN_MONITOR_RWMP			  0x04
110#define     AXEN_MONITOR_RWWF			  0x08
111#define     AXEN_MONITOR_RW_FLAG		  0x10
112#define     AXEN_MONITOR_PMEPOL			  0x20
113#define     AXEN_MONITOR_PMETYPE		  0x40
114#define   AXEN_UNK_28				0x28
115#define   AXEN_PHYCLK				0x33
116#define     AXEN_PHYCLK_BCS			  0x01
117#define     AXEN_PHYCLK_ACS			  0x02
118#define     AXEN_PHYCLK_ULR			  0x08
119#define     AXEN_PHYCLK_ACSREQ			  0x10
120#define   AXEN_RX_COE				0x34
121#define	    AXEN_RXCOE_OFF			  0x00
122#define	    AXEN_RXCOE_IPv4			  0x01
123#define	    AXEN_RXCOE_TCPv4			  0x02
124#define	    AXEN_RXCOE_UDPv4			  0x04
125#define	    AXEN_RXCOE_ICMP			  0x08
126#define	    AXEN_RXCOE_IGMP			  0x10
127#define	    AXEN_RXCOE_TCPv6			  0x20
128#define	    AXEN_RXCOE_UDPv6			  0x40
129#define	    AXEN_RXCOE_ICMPv6			  0x80
130#define   AXEN_TX_COE				0x35
131#define	    AXEN_TXCOE_OFF			  0x00
132#define	    AXEN_TXCOE_IPv4			  0x01
133#define	    AXEN_TXCOE_TCPv4			  0x02
134#define	    AXEN_TXCOE_UDPv4			  0x04
135#define	    AXEN_TXCOE_ICMP			  0x08
136#define	    AXEN_TXCOE_IGMP			  0x10
137#define	    AXEN_TXCOE_TCPv6			  0x20
138#define	    AXEN_TXCOE_UDPv6			  0x40
139#define	    AXEN_TXCOE_ICMPv6			  0x80
140#define   AXEN_PAUSE_HIGH_WATERMARK		0x54
141#define   AXEN_PAUSE_LOW_WATERMARK		0x55
142
143
144/*   2byte cmd   */
145#define AXEN_CMD_MAC_READ2			0x2001
146#define AXEN_CMD_MAC_WRITE2			0x2101
147
148#define   AXEN_MAC_RXCTL			0x0b
149#define     AXEN_RXCTL_STOP			  0x0000
150#define     AXEN_RXCTL_PROMISC			  0x0001
151#define     AXEN_RXCTL_ACPT_ALL_MCAST		  0x0002
152#define     AXEN_RXCTL_HA8B			  0x0004
153#define     AXEN_RXCTL_AUTOB			  0x0008
154#define     AXEN_RXCTL_ACPT_BCAST		  0x0010
155#define     AXEN_RXCTL_ACPT_PHY_MCAST		  0x0020
156#define     AXEN_RXCTL_START			  0x0080
157#define     AXEN_RXCTL_DROPCRCERR		  0x0100
158#define     AXEN_RXCTL_IPE			  0x0200
159#define     AXEN_RXCTL_TXPADCRC			  0x0400
160#define   AXEN_MEDIUM_STATUS			0x22
161#define	    AXEN_MEDIUM_NONE			  0x0000
162#define	    AXEN_MEDIUM_GIGA			  0x0001
163#define	    AXEN_MEDIUM_FDX			  0x0002
164#define	    AXEN_MEDIUM_ALWAYS_ONE		  0x0004
165#define	    AXEN_MEDIUM_EN_125MHZ		  0x0008
166#define	    AXEN_MEDIUM_RXFLOW_CTRL_EN		  0x0010
167#define	    AXEN_MEDIUM_TXFLOW_CTRL_EN		  0x0020
168#define	    AXEN_MEDIUM_RECV_EN			  0x0100
169#define	    AXEN_MEDIUM_PS			  0x0200
170#define	    AXEN_MEDIUM_JUMBO_EN		  0x8040
171#define   AXEN_PHYPWR_RSTCTL			0x26
172#define     AXEN_PHYPWR_RSTCTL_BZ		  0x0010
173#define     AXEN_PHYPWR_RSTCTL_IPRL		  0x0020
174#define     AXEN_PHYPWR_RSTCTL_AUTODETACH	  0x1000
175
176#define AXEN_CMD_EEPROM_READ			0x2004
177#define	    AXEN_EEPROM_STAT			  0x43
178
179/*   5byte cmd   */
180#define AXEN_CMD_MAC_SET_RXSR			0x5101
181#define   AXEN_RX_BULKIN_QCTRL			  0x2e
182
183/*   6byte cmd   */
184#define AXEN_CMD_MAC_READ_ETHER			0x6001
185#define AXEN_CMD_MAC_WRITE_ETHER		0x6101
186#define   AXEN_CMD_MAC_NODE_ID			  0x10
187
188/*   8byte cmd   */
189#define AXEN_CMD_MAC_READ_FILTER		0x8001
190#define AXEN_CMD_MAC_WRITE_FILTER		0x8101
191#define   AXEN_FILTER_MULTI		 	  0x16
192
193/* ---PHY--- */
194/*   2byte cmd   */
195#define AXEN_CMD_MII_READ_REG			0x2002
196#define AXEN_CMD_MII_WRITE_REG			0x2102
197
198
199
200/* ========= */
201#define AXEN_GPIO0_EN		0x01
202#define AXEN_GPIO0		0x02
203#define AXEN_GPIO1_EN		0x04
204#define AXEN_GPIO1		0x08
205#define AXEN_GPIO2_EN		0x10
206#define AXEN_GPIO2		0x20
207#define AXEN_GPIO_RELOAD_EEPROM	0x80
208
209
210#define AXEN_TIMEOUT		1000
211
212#define AXEN_RX_LIST_CNT		1
213#define AXEN_TX_LIST_CNT		1
214
215
216/*
217 * The interrupt endpoint is currently unused
218 * by the ASIX part.
219 */
220#define AXEN_ENDPT_RX		0x0
221#define AXEN_ENDPT_TX		0x1
222#define AXEN_ENDPT_INTR		0x2
223#define AXEN_ENDPT_MAX		0x3
224
225struct axen_type {
226	struct usb_devno	axen_dev;
227	u_int16_t		axen_flags;
228#define AX178A	0x0001		/* AX88178a */
229#define AX179	0x0002		/* AX88179 */
230#define AX179A	0x0004		/* AX88179a */
231};
232
233struct axen_softc;
234
235struct axen_chain {
236	struct axen_softc	*axen_sc;
237	struct usbd_xfer	*axen_xfer;
238	char			*axen_buf;
239	struct mbuf		*axen_mbuf;
240	int			axen_accum;
241	int			axen_idx;
242};
243
244struct axen_cdata {
245	struct axen_chain	axen_tx_chain[AXEN_TX_LIST_CNT];
246	struct axen_chain	axen_rx_chain[AXEN_RX_LIST_CNT];
247	int			axen_tx_prod;
248	int			axen_tx_cons;
249	int			axen_tx_cnt;
250	int			axen_rx_prod;
251};
252
253struct axen_qctrl {
254	u_int8_t		ctrl;
255	u_int8_t		timer_low;
256	u_int8_t		timer_high;
257	u_int8_t		bufsize;
258	u_int8_t		ifg;
259} __packed;
260
261struct axen_sframe_hdr {
262	u_int32_t		plen; /* packet length */
263	u_int32_t		gso;
264} __packed;
265
266struct axen_softc {
267	struct device		axen_dev;
268#define GET_MII(sc) (&(sc)->axen_mii)
269	struct arpcom		arpcom;
270#define GET_IFP(sc) (&(sc)->arpcom.ac_if)
271	struct mii_data		axen_mii;
272	struct usbd_device	*axen_udev;
273	struct usbd_interface	*axen_iface;
274
275	u_int16_t		axen_vendor;
276	u_int16_t		axen_product;
277
278	u_int16_t		axen_flags;
279
280	int			axen_ed[AXEN_ENDPT_MAX];
281	struct usbd_pipe	*axen_ep[AXEN_ENDPT_MAX];
282	int			axen_unit;
283	struct axen_cdata	axen_cdata;
284	struct timeout		axen_stat_ch;
285
286	int			axen_refcnt;
287
288	struct usb_task		axen_tick_task;
289	struct usb_task		axen_stop_task;
290
291	struct rwlock		axen_mii_lock;
292
293	int			axen_link;
294	unsigned char		axen_ipgs[3];
295	int			axen_phyno;
296	struct timeval		axen_rx_notice;
297	u_int			axen_bufsz;
298	int			axen_rev;
299};
300