1/* $OpenBSD: pciide_hpt_reg.h,v 1.11 2010/07/23 07:47:13 jsg Exp $ */ 2/* $NetBSD: pciide_hpt_reg.h,v 1.4 2001/07/23 14:55:27 bouyer Exp $ */ 3 4/* 5 * Copyright (c) 2000 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef _DEV_PCI_PCIIDE_HPT_REG_H_ 30#define _DEV_PCI_PCIIDE_HPT_REG_H_ 31 32/* 33 * Register definitions for Highpoint PCI IDE controllers. 34 * 35 * The HPT366 has 2 PCI IDE functions, each of them has only one channel. 36 * The HPT370 and HPT372 has the 2 channels on the same PCI IDE function. 37 */ 38 39/* 40 * The HPT366, HPT370 and HPT372 have the same vendor/device ID but not the 41 * same revision. 42 */ 43#define HPT366_REV 0x01 44#define HPT370_REV 0x03 45#define HPT370A_REV 0x04 46#define HPT372_REV 0x05 47#define HPT374_REV 0x07 48 49#define HPT_IDETIM(chan, drive) (0x40 + ((drive) * 4) + ((chan) * 8)) 50#define HPT_IDETIM_BUFEN 0x80000000 51#define HPT_IDETIM_MSTEN 0x40000000 52#define HPT_IDETIM_DMAEN 0x20000000 53#define HPT_IDETIM_UDMAEN 0x10000000 54 55#define HPT366_CTRL1 0x50 56#define HPT366_CTRL1_BLKDIS(chan) (0x40 << (chan)) 57#define HPT366_CTRL1_CHANEN(chan) (0x10 << (chan)) 58#define HPT366_CTRL1_CLRBUF(chan) (0x04 << (chan)) 59#define HPT366_CTRL1_LEG(chan) (0x01 << (chan)) 60 61#define HPT366_CTRL2 0x51 62#define HPT366_CTRL2_FASTIRQ 0x80 63#define HPT366_CTRL2_HOLDIRQ(chan) (0x20 << (chan)) 64#define HPT366_CTRL2_SGEN 0x10 65#define HPT366_CTRL2_CLEARFIFO(chan) (0x04 << (chan)) 66#define HPT366_CTRL2_CLEARBMSM 0x02 67#define HPT366_CTRL2_CLEARSG 0x01 68 69#define HPT366_CTRL3(chan) (0x52 + ((chan) * 4)) 70#define HPT366_CTRL3_PDMA 0x8000 71#define HPT366_CTRL3_BP 0x4000 72#define HPT366_CTRL3_FASTIRQ_OFFSET 9 73#define HPT366_CTRL3_FASTIRQ_MASK 0x3 74 75#define HPT370_CTRL1(chan) (0x50 + ((chan) * 4)) 76#define HPT370_CTRL1_CLRSG 0x80 77#define HPT370_CTRL1_READF 0x40 78#define HPT370_CTRL1_CLRST 0x20 79#define HPT370_CTRL1_CLRSGC 0x10 80#define HPT370_CTRL1_BLKDIS 0x08 81#define HPT370_CTRL1_EN 0x04 82#define HPT370_CTRL1_CLRDBUF 0x02 83#define HPT370_CTRL1_LEGEN 0x01 84 85#define HPT370_CTRL2(chan) (0x51 + ((chan) * 4)) 86#define HPT370_CTRL2_FASTIRQ 0x02 87#define HPT370_CTRL2_HIRQ 0x01 88 89#define HPT370_CTRL3(chan) (0x52 + ((chan) * 4)) 90#define HPT370_CTRL3_HIZ 0x8000 91#define HPT370_CTRL3_BP 0x4000 92#define HPT370_CTRL3_FASTIRQ_OFFSET 9 93#define HPT370_CTRL3_FASTIRQ_MASK 0x3 94 95#define HPT_STAT1 0x58 96#define HPT_STAT1_IRQPOLL(chan) (0x40 << (chan)) /* 366 only */ 97#define HPT_STAT1_DMARQ(chan) (0x04 << ((chan) * 3)) 98#define HPT_STAT1_DMACK(chan) (0x02 << ((chan) * 3)) 99#define HPT_STAT1_IORDY(chan) (0x01 << ((chan) * 3)) 100 101#define HPT_STAT2 0x59 102#define HPT_STAT2_FLT_RST 0x40 /* 366 only */ 103#define HPT_STAT2_RST(chan) (0x40 << (chan)) /* 370 only */ 104#define HPT_STAT2_POLLEN(chan) (0x04 << ((chan) * 3)) 105#define HPT_STAT2_IRQD1(chan) (0x02 << ((chan) * 3)) 106#define HPT_STAT2_IRQD0_CH1 0x08 107#define HPT_STAT2_POLLST 0x01 108 109#define HPT_CSEL 0x5a 110#define HPT_CSEL_IRQDIS 0x10 /* 370 only */ 111#define HPT_CSEL_PCIDIS 0x08 /* 370 only */ 112#define HPT_CSEL_PCIWR 0x04 /* 370 only */ 113#define HPT_CSEL_CBLID(chan) (0x01 << (1 - (chan))) 114 115#define HPT_SC2 0x5b 116#define HPT_SC2_OSC_OK 0x80 117#define HPT_SC2_OSC_EN 0x20 118#define HPT_SC2_ECLK 0x10 119#define HPT_SC2_BPIO 0x08 120#define HPT_SC2_DMARQW 0x04 121#define HPT_SC2_SCLK 0x02 122#define HPT_SC2_MAEN 0x01 123 124static u_int32_t hpt366_pio[] = 125 {0x00d0a7aa, 0x00c8a753, 0x00c8a742, 0x00c8a731}; 126static u_int32_t hpt366_dma[] = 127 {0x20c8a797, 0x20c8a742, 0x20c8a731}; 128static u_int32_t hpt366_udma[] = 129 {0x10c8a731, 0x10cba731, 0x10caa731, 0x10cfa731, 0x10c9a731}; 130 131static u_int32_t hpt370_pio[] = 132 {0x06914e8a, 0x06914e65, 0x06514e33, 0x06514e22, 0x06514e21}; 133static u_int32_t hpt370_dma[] = 134 {0x26514e97, 0x26514e33, 0x26514e21}; 135static u_int32_t hpt370_udma[] = 136 {0x16514e31, 0x164d4e31, 0x16494e31, 0x166d4e31, 0x16454e31, 137 0x16454e31}; 138 139static u_int32_t hpt372_pio[] = 140 {0x0d029d5e, 0x0d029d26, 0x0c829ca6, 0x0c829c84, 0x0c829c62}; 141static u_int32_t hpt372_dma[] = 142 {0x2c82922e, 0x2c829266, 0x2c829262}; 143static u_int32_t hpt372_udma[] = 144 {0x1c82dc62, 0x1c9adc62, 0x1c91dc62, 0x1c8edc62, 0x1c8ddc62, 145 0x1c6ddc62, 0x1c81dc62}; 146 147static u_int32_t hpt374_pio[] = 148 {0x0ac1f48a, 0x0ac1f465, 0x0a81f454, 0x0a81f443, 0x0a81f442}; 149static u_int32_t hpt374_dma[] = 150 {0x228082ea, 0x22808254, 0x22808242}; 151static u_int32_t hpt374_udma[] = 152 {0x121882ea, 0x12148254, 0x120c8242, 0x128c8242, 0x12ac8242, 153 0x12848242, 0x12808242}; 154 155#endif /* !_DEV_PCI_PCIIDE_HPT_REG_H_ */ 156