Searched refs:gfx (Results 76 - 93 of 93) sorted by relevance

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/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_v2_5.c562 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
1050 adev->gfx.config.gb_addr_config);
1052 adev->gfx.config.gb_addr_config);
H A Damdgpu_vm.c603 if (adev->gfx.mec_fw_version < 673)
713 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
714 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
H A Dvcn_v4_0.c531 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
1124 adev->gfx.config.gb_addr_config);
H A Dvcn_v2_0.c384 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
480 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
H A Damdgpu_cik_sdma.c85 * and gfx. There are two DMA engines (SDMA0, SDMA1)
86 * and each one supports 1 ring buffer used for gfx
300 * cik_sdma_gfx_stop - stop the gfx async dma engines
304 * Stop the gfx async dma ring buffers (CIK).
423 * Set up the gfx DMA ring buffers and enable them (CIK).
448 adev->gfx.config.gb_addr_config & 0x70);
583 /* start the gfx rings and rlc compute queues */
H A Dsdma_v2_4.c84 * and gfx. There are two DMA engines (SDMA0, SDMA1)
85 * and each one supports 1 ring buffer used for gfx
331 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
335 * Stop the gfx async dma ring buffers (VI).
399 * Set up the gfx DMA ring buffers and enable them (VI).
423 adev->gfx.config.gb_addr_config & 0x70);
515 /* start the gfx rings and rlc compute queues */
H A Damdgpu_acpi.c1377 adev->gfx.imu.funcs) /* Not need to do mode2 reset for IMU enabled APUs */
H A Dvcn_v3_0.c591 UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
1178 adev->gfx.config.gb_addr_config);
H A Damdgpu_ras.c60 "gfx",
341 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
425 * The block is one of: umc, sdma, gfx, etc.
450 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
585 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
782 /* Only enable gfx ras feature from host side */
857 /* gfx block ras dsiable cmd must send to ras-ta */
863 /* clean gfx block ras features flag */
2458 * force enable gfx ra
[all...]
H A Dsdma_v3_0.c185 * and gfx. There are two DMA engines (SDMA0, SDMA1)
186 * and each one supports 1 ring buffer used for gfx
505 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
509 * Stop the gfx async dma ring buffers (VI).
634 * Set up the gfx DMA ring buffers and enable them (VI).
661 adev->gfx.config.gb_addr_config & 0x70);
787 /* start the gfx rings and rlc compute queues */
H A Damdgpu.h959 /* gfx */
960 struct amdgpu_gfx gfx; member in struct:amdgpu_device
H A Damdgpu_ttm.c851 int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/
H A Damdgpu_smu.c173 dev_err(adev->dev, "Failed to enable gfx imu!\n");
267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
1534 * - As the gfx related features are under control of
1608 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
1609 adev->gfx.rlc.funcs->stop(adev);
1718 adev->gfx.gfx_off_entrycount = count;
1808 /* enter umd pstate, save current level, disable gfx cg*/
1817 /* exit umd pstate, restore level, enable gfx cg*/
2975 dev_err(smu->adev->dev, "enable gfx features failed!\n");
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c1911 adev->gfx.cu_info.number,
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c430 data->total_active_cus = adev->gfx.cu_info.number;
2274 "Attempt to get current gfx clk Failed!",
2279 "Attempt to get gfx clk levels Failed!",
H A Dsmu7_powertune.c966 num_se = adev->gfx.config.max_shader_engines;
H A Dvega20_hwmgr.c472 data->total_active_cus = adev->gfx.cu_info.number;
3375 "Attempt to get current gfx clk Failed!",
H A Dvega10_hwmgr.c914 data->total_active_cus = adev->gfx.cu_info.number;
3199 /* under vega10 pp one vf mode, the gfx clk dpm need be lower
4201 /* under vega10 pp one vf mode, the gfx clk dpm need be lower

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