1/* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24#include <linux/debugfs.h> 25#include <linux/list.h> 26#include <linux/module.h> 27#include <linux/uaccess.h> 28#include <linux/reboot.h> 29#include <linux/syscalls.h> 30#include <linux/pm_runtime.h> 31 32#include "amdgpu.h" 33#include "amdgpu_ras.h" 34#include "amdgpu_atomfirmware.h" 35#include "amdgpu_xgmi.h" 36#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 37#include "nbio_v4_3.h" 38#include "nbio_v7_9.h" 39#include "atom.h" 40#include "amdgpu_reset.h" 41 42#ifdef CONFIG_X86_MCE_AMD 43#include <asm/mce.h> 44 45static bool notifier_registered; 46#endif 47static const char *RAS_FS_NAME = "ras"; 48 49const char *ras_error_string[] = { 50 "none", 51 "parity", 52 "single_correctable", 53 "multi_uncorrectable", 54 "poison", 55}; 56 57const char *ras_block_string[] = { 58 "umc", 59 "sdma", 60 "gfx", 61 "mmhub", 62 "athub", 63 "pcie_bif", 64 "hdp", 65 "xgmi_wafl", 66 "df", 67 "smn", 68 "sem", 69 "mp0", 70 "mp1", 71 "fuse", 72 "mca", 73 "vcn", 74 "jpeg", 75}; 76 77const char *ras_mca_block_string[] = { 78 "mca_mp0", 79 "mca_mp1", 80 "mca_mpio", 81 "mca_iohc", 82}; 83 84struct amdgpu_ras_block_list { 85 /* ras block link */ 86 struct list_head node; 87 88 struct amdgpu_ras_block_object *ras_obj; 89}; 90 91const char *get_ras_block_str(struct ras_common_if *ras_block) 92{ 93 if (!ras_block) 94 return "NULL"; 95 96 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT) 97 return "OUT OF RANGE"; 98 99 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) 100 return ras_mca_block_string[ras_block->sub_block_index]; 101 102 return ras_block_string[ras_block->block]; 103} 104 105#define ras_block_str(_BLOCK_) \ 106 (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range") 107 108#define ras_err_str(i) (ras_error_string[ffs(i)]) 109 110#define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) 111 112/* inject address is 52 bits */ 113#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) 114 115/* typical ECC bad page rate is 1 bad page per 100MB VRAM */ 116#define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL) 117 118enum amdgpu_ras_retire_page_reservation { 119 AMDGPU_RAS_RETIRE_PAGE_RESERVED, 120 AMDGPU_RAS_RETIRE_PAGE_PENDING, 121 AMDGPU_RAS_RETIRE_PAGE_FAULT, 122}; 123 124atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); 125 126static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, 127 uint64_t addr); 128static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, 129 uint64_t addr); 130#ifdef CONFIG_X86_MCE_AMD 131static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); 132struct mce_notifier_adev_list { 133 struct amdgpu_device *devs[MAX_GPU_INSTANCE]; 134 int num_gpu; 135}; 136static struct mce_notifier_adev_list mce_adev_list; 137#endif 138 139void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) 140{ 141 if (adev && amdgpu_ras_get_context(adev)) 142 amdgpu_ras_get_context(adev)->error_query_ready = ready; 143} 144 145static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) 146{ 147 if (adev && amdgpu_ras_get_context(adev)) 148 return amdgpu_ras_get_context(adev)->error_query_ready; 149 150 return false; 151} 152 153static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) 154{ 155 struct ras_err_data err_data = {0, 0, 0, NULL}; 156 struct eeprom_table_record err_rec; 157 158 if ((address >= adev->gmc.mc_vram_size) || 159 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { 160 dev_warn(adev->dev, 161 "RAS WARN: input address 0x%llx is invalid.\n", 162 address); 163 return -EINVAL; 164 } 165 166 if (amdgpu_ras_check_bad_page(adev, address)) { 167 dev_warn(adev->dev, 168 "RAS WARN: 0x%llx has already been marked as bad page!\n", 169 address); 170 return 0; 171 } 172 173 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); 174 err_data.err_addr = &err_rec; 175 amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0); 176 177 if (amdgpu_bad_page_threshold != 0) { 178 amdgpu_ras_add_bad_pages(adev, err_data.err_addr, 179 err_data.err_addr_cnt); 180 amdgpu_ras_save_bad_pages(adev, NULL); 181 } 182 183 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"); 184 dev_warn(adev->dev, "Clear EEPROM:\n"); 185 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); 186 187 return 0; 188} 189 190#ifdef __linux__ 191 192static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, 193 size_t size, loff_t *pos) 194{ 195 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; 196 struct ras_query_if info = { 197 .head = obj->head, 198 }; 199 ssize_t s; 200 char val[128]; 201 202 if (amdgpu_ras_query_error_status(obj->adev, &info)) 203 return -EINVAL; 204 205 /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */ 206 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && 207 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) { 208 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) 209 dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); 210 } 211 212 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", 213 "ue", info.ue_count, 214 "ce", info.ce_count); 215 if (*pos >= s) 216 return 0; 217 218 s -= *pos; 219 s = min_t(u64, s, size); 220 221 222 if (copy_to_user(buf, &val[*pos], s)) 223 return -EINVAL; 224 225 *pos += s; 226 227 return s; 228} 229 230static const struct file_operations amdgpu_ras_debugfs_ops = { 231 .owner = THIS_MODULE, 232 .read = amdgpu_ras_debugfs_read, 233 .write = NULL, 234 .llseek = default_llseek 235}; 236 237static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) 238{ 239 int i; 240 241 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { 242 *block_id = i; 243 if (strcmp(name, ras_block_string[i]) == 0) 244 return 0; 245 } 246 return -EINVAL; 247} 248 249static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, 250 const char __user *buf, size_t size, 251 loff_t *pos, struct ras_debug_if *data) 252{ 253 ssize_t s = min_t(u64, 64, size); 254 char str[65]; 255 char block_name[33]; 256 char err[9] = "ue"; 257 int op = -1; 258 int block_id; 259 uint32_t sub_block; 260 u64 address, value; 261 /* default value is 0 if the mask is not set by user */ 262 u32 instance_mask = 0; 263 264 if (*pos) 265 return -EINVAL; 266 *pos = size; 267 268 memset(str, 0, sizeof(str)); 269 memset(data, 0, sizeof(*data)); 270 271 if (copy_from_user(str, buf, s)) 272 return -EINVAL; 273 274 if (sscanf(str, "disable %32s", block_name) == 1) 275 op = 0; 276 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) 277 op = 1; 278 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) 279 op = 2; 280 else if (strstr(str, "retire_page") != NULL) 281 op = 3; 282 else if (str[0] && str[1] && str[2] && str[3]) 283 /* ascii string, but commands are not matched. */ 284 return -EINVAL; 285 286 if (op != -1) { 287 if (op == 3) { 288 if (sscanf(str, "%*s 0x%llx", &address) != 1 && 289 sscanf(str, "%*s %llu", &address) != 1) 290 return -EINVAL; 291 292 data->op = op; 293 data->inject.address = address; 294 295 return 0; 296 } 297 298 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) 299 return -EINVAL; 300 301 data->head.block = block_id; 302 /* only ue and ce errors are supported */ 303 if (!memcmp("ue", err, 2)) 304 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 305 else if (!memcmp("ce", err, 2)) 306 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; 307 else 308 return -EINVAL; 309 310 data->op = op; 311 312 if (op == 2) { 313 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x", 314 &sub_block, &address, &value, &instance_mask) != 4 && 315 sscanf(str, "%*s %*s %*s %u %llu %llu %u", 316 &sub_block, &address, &value, &instance_mask) != 4 && 317 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", 318 &sub_block, &address, &value) != 3 && 319 sscanf(str, "%*s %*s %*s %u %llu %llu", 320 &sub_block, &address, &value) != 3) 321 return -EINVAL; 322 data->head.sub_block_index = sub_block; 323 data->inject.address = address; 324 data->inject.value = value; 325 data->inject.instance_mask = instance_mask; 326 } 327 } else { 328 if (size < sizeof(*data)) 329 return -EINVAL; 330 331 if (copy_from_user(data, buf, sizeof(*data))) 332 return -EINVAL; 333 } 334 335 return 0; 336} 337 338static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev, 339 struct ras_debug_if *data) 340{ 341 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; 342 uint32_t mask, inst_mask = data->inject.instance_mask; 343 344 /* no need to set instance mask if there is only one instance */ 345 if (num_xcc <= 1 && inst_mask) { 346 data->inject.instance_mask = 0; 347 dev_dbg(adev->dev, 348 "RAS inject mask(0x%x) isn't supported and force it to 0.\n", 349 inst_mask); 350 351 return; 352 } 353 354 switch (data->head.block) { 355 case AMDGPU_RAS_BLOCK__GFX: 356 mask = GENMASK(num_xcc - 1, 0); 357 break; 358 case AMDGPU_RAS_BLOCK__SDMA: 359 mask = GENMASK(adev->sdma.num_instances - 1, 0); 360 break; 361 case AMDGPU_RAS_BLOCK__VCN: 362 case AMDGPU_RAS_BLOCK__JPEG: 363 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0); 364 break; 365 default: 366 mask = inst_mask; 367 break; 368 } 369 370 /* remove invalid bits in instance mask */ 371 data->inject.instance_mask &= mask; 372 if (inst_mask != data->inject.instance_mask) 373 dev_dbg(adev->dev, 374 "Adjust RAS inject mask 0x%x to 0x%x\n", 375 inst_mask, data->inject.instance_mask); 376} 377 378/** 379 * DOC: AMDGPU RAS debugfs control interface 380 * 381 * The control interface accepts struct ras_debug_if which has two members. 382 * 383 * First member: ras_debug_if::head or ras_debug_if::inject. 384 * 385 * head is used to indicate which IP block will be under control. 386 * 387 * head has four members, they are block, type, sub_block_index, name. 388 * block: which IP will be under control. 389 * type: what kind of error will be enabled/disabled/injected. 390 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. 391 * name: the name of IP. 392 * 393 * inject has three more members than head, they are address, value and mask. 394 * As their names indicate, inject operation will write the 395 * value to the address. 396 * 397 * The second member: struct ras_debug_if::op. 398 * It has three kinds of operations. 399 * 400 * - 0: disable RAS on the block. Take ::head as its data. 401 * - 1: enable RAS on the block. Take ::head as its data. 402 * - 2: inject errors on the block. Take ::inject as its data. 403 * 404 * How to use the interface? 405 * 406 * In a program 407 * 408 * Copy the struct ras_debug_if in your code and initialize it. 409 * Write the struct to the control interface. 410 * 411 * From shell 412 * 413 * .. code-block:: bash 414 * 415 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl 416 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl 417 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl 418 * 419 * Where N, is the card which you want to affect. 420 * 421 * "disable" requires only the block. 422 * "enable" requires the block and error type. 423 * "inject" requires the block, error type, address, and value. 424 * 425 * The block is one of: umc, sdma, gfx, etc. 426 * see ras_block_string[] for details 427 * 428 * The error type is one of: ue, ce, where, 429 * ue is multi-uncorrectable 430 * ce is single-correctable 431 * 432 * The sub-block is a the sub-block index, pass 0 if there is no sub-block. 433 * The address and value are hexadecimal numbers, leading 0x is optional. 434 * The mask means instance mask, is optional, default value is 0x1. 435 * 436 * For instance, 437 * 438 * .. code-block:: bash 439 * 440 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl 441 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl 442 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl 443 * 444 * How to check the result of the operation? 445 * 446 * To check disable/enable, see "ras" features at, 447 * /sys/class/drm/card[0/1/2...]/device/ras/features 448 * 449 * To check inject, see the corresponding error count at, 450 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count 451 * 452 * .. note:: 453 * Operations are only allowed on blocks which are supported. 454 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask 455 * to see which blocks support RAS on a particular asic. 456 * 457 */ 458static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, 459 const char __user *buf, 460 size_t size, loff_t *pos) 461{ 462 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 463 struct ras_debug_if data; 464 int ret = 0; 465 466 if (!amdgpu_ras_get_error_query_ready(adev)) { 467 dev_warn(adev->dev, "RAS WARN: error injection " 468 "currently inaccessible\n"); 469 return size; 470 } 471 472 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); 473 if (ret) 474 return ret; 475 476 if (data.op == 3) { 477 ret = amdgpu_reserve_page_direct(adev, data.inject.address); 478 if (!ret) 479 return size; 480 else 481 return ret; 482 } 483 484 if (!amdgpu_ras_is_supported(adev, data.head.block)) 485 return -EINVAL; 486 487 switch (data.op) { 488 case 0: 489 ret = amdgpu_ras_feature_enable(adev, &data.head, 0); 490 break; 491 case 1: 492 ret = amdgpu_ras_feature_enable(adev, &data.head, 1); 493 break; 494 case 2: 495 if ((data.inject.address >= adev->gmc.mc_vram_size && 496 adev->gmc.mc_vram_size) || 497 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { 498 dev_warn(adev->dev, "RAS WARN: input address " 499 "0x%llx is invalid.", 500 data.inject.address); 501 ret = -EINVAL; 502 break; 503 } 504 505 /* umc ce/ue error injection for a bad page is not allowed */ 506 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && 507 amdgpu_ras_check_bad_page(adev, data.inject.address)) { 508 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has " 509 "already been marked as bad!\n", 510 data.inject.address); 511 break; 512 } 513 514 amdgpu_ras_instance_mask_check(adev, &data); 515 516 /* data.inject.address is offset instead of absolute gpu address */ 517 ret = amdgpu_ras_error_inject(adev, &data.inject); 518 break; 519 default: 520 ret = -EINVAL; 521 break; 522 } 523 524 if (ret) 525 return ret; 526 527 return size; 528} 529 530/** 531 * DOC: AMDGPU RAS debugfs EEPROM table reset interface 532 * 533 * Some boards contain an EEPROM which is used to persistently store a list of 534 * bad pages which experiences ECC errors in vram. This interface provides 535 * a way to reset the EEPROM, e.g., after testing error injection. 536 * 537 * Usage: 538 * 539 * .. code-block:: bash 540 * 541 * echo 1 > ../ras/ras_eeprom_reset 542 * 543 * will reset EEPROM table to 0 entries. 544 * 545 */ 546static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, 547 const char __user *buf, 548 size_t size, loff_t *pos) 549{ 550 struct amdgpu_device *adev = 551 (struct amdgpu_device *)file_inode(f)->i_private; 552 int ret; 553 554 ret = amdgpu_ras_eeprom_reset_table( 555 &(amdgpu_ras_get_context(adev)->eeprom_control)); 556 557 if (!ret) { 558 /* Something was written to EEPROM. 559 */ 560 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; 561 return size; 562 } else { 563 return ret; 564 } 565} 566 567static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { 568 .owner = THIS_MODULE, 569 .read = NULL, 570 .write = amdgpu_ras_debugfs_ctrl_write, 571 .llseek = default_llseek 572}; 573 574static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { 575 .owner = THIS_MODULE, 576 .read = NULL, 577 .write = amdgpu_ras_debugfs_eeprom_write, 578 .llseek = default_llseek 579}; 580 581/** 582 * DOC: AMDGPU RAS sysfs Error Count Interface 583 * 584 * It allows the user to read the error count for each IP block on the gpu through 585 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count 586 * 587 * It outputs the multiple lines which report the uncorrected (ue) and corrected 588 * (ce) error counts. 589 * 590 * The format of one line is below, 591 * 592 * [ce|ue]: count 593 * 594 * Example: 595 * 596 * .. code-block:: bash 597 * 598 * ue: 0 599 * ce: 1 600 * 601 */ 602static ssize_t amdgpu_ras_sysfs_read(struct device *dev, 603 struct device_attribute *attr, char *buf) 604{ 605 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); 606 struct ras_query_if info = { 607 .head = obj->head, 608 }; 609 610 if (!amdgpu_ras_get_error_query_ready(obj->adev)) 611 return sysfs_emit(buf, "Query currently inaccessible\n"); 612 613 if (amdgpu_ras_query_error_status(obj->adev, &info)) 614 return -EINVAL; 615 616 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && 617 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) { 618 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) 619 dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); 620 } 621 622 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, 623 "ce", info.ce_count); 624} 625 626#endif /* __linux__ */ 627 628/* obj begin */ 629 630#define get_obj(obj) do { (obj)->use++; } while (0) 631#define alive_obj(obj) ((obj)->use) 632 633static inline void put_obj(struct ras_manager *obj) 634{ 635 if (obj && (--obj->use == 0)) 636 list_del(&obj->node); 637 if (obj && (obj->use < 0)) 638 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head)); 639} 640 641/* make one obj and return it. */ 642static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, 643 struct ras_common_if *head) 644{ 645 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 646 struct ras_manager *obj; 647 648 if (!adev->ras_enabled || !con) 649 return NULL; 650 651 if (head->block >= AMDGPU_RAS_BLOCK_COUNT) 652 return NULL; 653 654 if (head->block == AMDGPU_RAS_BLOCK__MCA) { 655 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) 656 return NULL; 657 658 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; 659 } else 660 obj = &con->objs[head->block]; 661 662 /* already exist. return obj? */ 663 if (alive_obj(obj)) 664 return NULL; 665 666 obj->head = *head; 667 obj->adev = adev; 668 list_add(&obj->node, &con->head); 669 get_obj(obj); 670 671 return obj; 672} 673 674/* return an obj equal to head, or the first when head is NULL */ 675struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, 676 struct ras_common_if *head) 677{ 678 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 679 struct ras_manager *obj; 680 int i; 681 682 if (!adev->ras_enabled || !con) 683 return NULL; 684 685 if (head) { 686 if (head->block >= AMDGPU_RAS_BLOCK_COUNT) 687 return NULL; 688 689 if (head->block == AMDGPU_RAS_BLOCK__MCA) { 690 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) 691 return NULL; 692 693 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; 694 } else 695 obj = &con->objs[head->block]; 696 697 if (alive_obj(obj)) 698 return obj; 699 } else { 700 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { 701 obj = &con->objs[i]; 702 if (alive_obj(obj)) 703 return obj; 704 } 705 } 706 707 return NULL; 708} 709/* obj end */ 710 711/* feature ctl begin */ 712static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, 713 struct ras_common_if *head) 714{ 715 return adev->ras_hw_enabled & BIT(head->block); 716} 717 718static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, 719 struct ras_common_if *head) 720{ 721 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 722 723 return con->features & BIT(head->block); 724} 725 726/* 727 * if obj is not created, then create one. 728 * set feature enable flag. 729 */ 730static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, 731 struct ras_common_if *head, int enable) 732{ 733 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 734 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); 735 736 /* If hardware does not support ras, then do not create obj. 737 * But if hardware support ras, we can create the obj. 738 * Ras framework checks con->hw_supported to see if it need do 739 * corresponding initialization. 740 * IP checks con->support to see if it need disable ras. 741 */ 742 if (!amdgpu_ras_is_feature_allowed(adev, head)) 743 return 0; 744 745 if (enable) { 746 if (!obj) { 747 obj = amdgpu_ras_create_obj(adev, head); 748 if (!obj) 749 return -EINVAL; 750 } else { 751 /* In case we create obj somewhere else */ 752 get_obj(obj); 753 } 754 con->features |= BIT(head->block); 755 } else { 756 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { 757 con->features &= ~BIT(head->block); 758 put_obj(obj); 759 } 760 } 761 762 return 0; 763} 764 765/* wrapper of psp_ras_enable_features */ 766int amdgpu_ras_feature_enable(struct amdgpu_device *adev, 767 struct ras_common_if *head, bool enable) 768{ 769 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 770 union ta_ras_cmd_input *info; 771 int ret; 772 773 if (!con) 774 return -EINVAL; 775 776 /* Do not enable ras feature if it is not allowed */ 777 if (enable && 778 head->block != AMDGPU_RAS_BLOCK__GFX && 779 !amdgpu_ras_is_feature_allowed(adev, head)) 780 return 0; 781 782 /* Only enable gfx ras feature from host side */ 783 if (head->block == AMDGPU_RAS_BLOCK__GFX && 784 !amdgpu_sriov_vf(adev) && 785 !amdgpu_ras_intr_triggered()) { 786 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); 787 if (!info) 788 return -ENOMEM; 789 790 if (!enable) { 791 info->disable_features = (struct ta_ras_disable_features_input) { 792 .block_id = amdgpu_ras_block_to_ta(head->block), 793 .error_type = amdgpu_ras_error_to_ta(head->type), 794 }; 795 } else { 796 info->enable_features = (struct ta_ras_enable_features_input) { 797 .block_id = amdgpu_ras_block_to_ta(head->block), 798 .error_type = amdgpu_ras_error_to_ta(head->type), 799 }; 800 } 801 802 ret = psp_ras_enable_features(&adev->psp, info, enable); 803 if (ret) { 804 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n", 805 enable ? "enable":"disable", 806 get_ras_block_str(head), 807 amdgpu_ras_is_poison_mode_supported(adev), ret); 808 kfree(info); 809 return ret; 810 } 811 812 kfree(info); 813 } 814 815 /* setup the obj */ 816 __amdgpu_ras_feature_enable(adev, head, enable); 817 818 return 0; 819} 820 821/* Only used in device probe stage and called only once. */ 822int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, 823 struct ras_common_if *head, bool enable) 824{ 825 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 826 int ret; 827 828 if (!con) 829 return -EINVAL; 830 831 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { 832 if (enable) { 833 /* There is no harm to issue a ras TA cmd regardless of 834 * the currecnt ras state. 835 * If current state == target state, it will do nothing 836 * But sometimes it requests driver to reset and repost 837 * with error code -EAGAIN. 838 */ 839 ret = amdgpu_ras_feature_enable(adev, head, 1); 840 /* With old ras TA, we might fail to enable ras. 841 * Log it and just setup the object. 842 * TODO need remove this WA in the future. 843 */ 844 if (ret == -EINVAL) { 845 ret = __amdgpu_ras_feature_enable(adev, head, 1); 846 if (!ret) 847 dev_info(adev->dev, 848 "RAS INFO: %s setup object\n", 849 get_ras_block_str(head)); 850 } 851 } else { 852 /* setup the object then issue a ras TA disable cmd.*/ 853 ret = __amdgpu_ras_feature_enable(adev, head, 1); 854 if (ret) 855 return ret; 856 857 /* gfx block ras dsiable cmd must send to ras-ta */ 858 if (head->block == AMDGPU_RAS_BLOCK__GFX) 859 con->features |= BIT(head->block); 860 861 ret = amdgpu_ras_feature_enable(adev, head, 0); 862 863 /* clean gfx block ras features flag */ 864 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX) 865 con->features &= ~BIT(head->block); 866 } 867 } else 868 ret = amdgpu_ras_feature_enable(adev, head, enable); 869 870 return ret; 871} 872 873static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, 874 bool bypass) 875{ 876 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 877 struct ras_manager *obj, *tmp; 878 879 list_for_each_entry_safe(obj, tmp, &con->head, node) { 880 /* bypass psp. 881 * aka just release the obj and corresponding flags 882 */ 883 if (bypass) { 884 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) 885 break; 886 } else { 887 if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) 888 break; 889 } 890 } 891 892 return con->features; 893} 894 895static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, 896 bool bypass) 897{ 898 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 899 int i; 900 const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE; 901 902 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { 903 struct ras_common_if head = { 904 .block = i, 905 .type = default_ras_type, 906 .sub_block_index = 0, 907 }; 908 909 if (i == AMDGPU_RAS_BLOCK__MCA) 910 continue; 911 912 if (bypass) { 913 /* 914 * bypass psp. vbios enable ras for us. 915 * so just create the obj 916 */ 917 if (__amdgpu_ras_feature_enable(adev, &head, 1)) 918 break; 919 } else { 920 if (amdgpu_ras_feature_enable(adev, &head, 1)) 921 break; 922 } 923 } 924 925 for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { 926 struct ras_common_if head = { 927 .block = AMDGPU_RAS_BLOCK__MCA, 928 .type = default_ras_type, 929 .sub_block_index = i, 930 }; 931 932 if (bypass) { 933 /* 934 * bypass psp. vbios enable ras for us. 935 * so just create the obj 936 */ 937 if (__amdgpu_ras_feature_enable(adev, &head, 1)) 938 break; 939 } else { 940 if (amdgpu_ras_feature_enable(adev, &head, 1)) 941 break; 942 } 943 } 944 945 return con->features; 946} 947/* feature ctl end */ 948 949static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj, 950 enum amdgpu_ras_block block) 951{ 952 if (!block_obj) 953 return -EINVAL; 954 955 if (block_obj->ras_comm.block == block) 956 return 0; 957 958 return -EINVAL; 959} 960 961static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev, 962 enum amdgpu_ras_block block, uint32_t sub_block_index) 963{ 964 struct amdgpu_ras_block_list *node, *tmp; 965 struct amdgpu_ras_block_object *obj; 966 967 if (block >= AMDGPU_RAS_BLOCK__LAST) 968 return NULL; 969 970 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { 971 if (!node->ras_obj) { 972 dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); 973 continue; 974 } 975 976 obj = node->ras_obj; 977 if (obj->ras_block_match) { 978 if (obj->ras_block_match(obj, block, sub_block_index) == 0) 979 return obj; 980 } else { 981 if (amdgpu_ras_block_match_default(obj, block) == 0) 982 return obj; 983 } 984 } 985 986 return NULL; 987} 988 989static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data) 990{ 991 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 992 int ret = 0; 993 994 /* 995 * choosing right query method according to 996 * whether smu support query error information 997 */ 998 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc)); 999 if (ret == -EOPNOTSUPP) { 1000 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && 1001 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) 1002 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); 1003 1004 /* umc query_ras_error_address is also responsible for clearing 1005 * error status 1006 */ 1007 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && 1008 adev->umc.ras->ras_block.hw_ops->query_ras_error_address) 1009 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data); 1010 } else if (!ret) { 1011 if (adev->umc.ras && 1012 adev->umc.ras->ecc_info_query_ras_error_count) 1013 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data); 1014 1015 if (adev->umc.ras && 1016 adev->umc.ras->ecc_info_query_ras_error_address) 1017 adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data); 1018 } 1019} 1020 1021/* query/inject/cure begin */ 1022int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 1023 struct ras_query_if *info) 1024{ 1025 struct amdgpu_ras_block_object *block_obj = NULL; 1026 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); 1027 struct ras_err_data err_data = {0, 0, 0, NULL}; 1028 1029 if (!obj) 1030 return -EINVAL; 1031 1032 if (!info || info->head.block == AMDGPU_RAS_BLOCK_COUNT) 1033 return -EINVAL; 1034 1035 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) { 1036 amdgpu_ras_get_ecc_info(adev, &err_data); 1037 } else { 1038 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0); 1039 if (!block_obj || !block_obj->hw_ops) { 1040 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", 1041 get_ras_block_str(&info->head)); 1042 return -EINVAL; 1043 } 1044 1045 if (block_obj->hw_ops->query_ras_error_count) 1046 block_obj->hw_ops->query_ras_error_count(adev, &err_data); 1047 1048 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) || 1049 (info->head.block == AMDGPU_RAS_BLOCK__GFX) || 1050 (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) { 1051 if (block_obj->hw_ops->query_ras_error_status) 1052 block_obj->hw_ops->query_ras_error_status(adev); 1053 } 1054 } 1055 1056 obj->err_data.ue_count += err_data.ue_count; 1057 obj->err_data.ce_count += err_data.ce_count; 1058 1059 info->ue_count = obj->err_data.ue_count; 1060 info->ce_count = obj->err_data.ce_count; 1061 1062 if (err_data.ce_count) { 1063 if (!adev->aid_mask && 1064 adev->smuio.funcs && 1065 adev->smuio.funcs->get_socket_id && 1066 adev->smuio.funcs->get_die_id) { 1067 dev_info(adev->dev, "socket: %d, die: %d " 1068 "%ld correctable hardware errors " 1069 "detected in %s block, no user " 1070 "action is needed.\n", 1071 adev->smuio.funcs->get_socket_id(adev), 1072 adev->smuio.funcs->get_die_id(adev), 1073 obj->err_data.ce_count, 1074 get_ras_block_str(&info->head)); 1075 } else { 1076 dev_info(adev->dev, "%ld correctable hardware errors " 1077 "detected in %s block, no user " 1078 "action is needed.\n", 1079 obj->err_data.ce_count, 1080 get_ras_block_str(&info->head)); 1081 } 1082 } 1083 if (err_data.ue_count) { 1084 if (!adev->aid_mask && 1085 adev->smuio.funcs && 1086 adev->smuio.funcs->get_socket_id && 1087 adev->smuio.funcs->get_die_id) { 1088 dev_info(adev->dev, "socket: %d, die: %d " 1089 "%ld uncorrectable hardware errors " 1090 "detected in %s block\n", 1091 adev->smuio.funcs->get_socket_id(adev), 1092 adev->smuio.funcs->get_die_id(adev), 1093 obj->err_data.ue_count, 1094 get_ras_block_str(&info->head)); 1095 } else { 1096 dev_info(adev->dev, "%ld uncorrectable hardware errors " 1097 "detected in %s block\n", 1098 obj->err_data.ue_count, 1099 get_ras_block_str(&info->head)); 1100 } 1101 } 1102 1103 return 0; 1104} 1105 1106int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 1107 enum amdgpu_ras_block block) 1108{ 1109 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0); 1110 1111 if (!amdgpu_ras_is_supported(adev, block)) 1112 return -EINVAL; 1113 1114 if (!block_obj || !block_obj->hw_ops) { 1115 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", 1116 ras_block_str(block)); 1117 return -EINVAL; 1118 } 1119 1120 if (block_obj->hw_ops->reset_ras_error_count) 1121 block_obj->hw_ops->reset_ras_error_count(adev); 1122 1123 if ((block == AMDGPU_RAS_BLOCK__GFX) || 1124 (block == AMDGPU_RAS_BLOCK__MMHUB)) { 1125 if (block_obj->hw_ops->reset_ras_error_status) 1126 block_obj->hw_ops->reset_ras_error_status(adev); 1127 } 1128 1129 return 0; 1130} 1131 1132/* wrapper of psp_ras_trigger_error */ 1133int amdgpu_ras_error_inject(struct amdgpu_device *adev, 1134 struct ras_inject_if *info) 1135{ 1136 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); 1137 struct ta_ras_trigger_error_input block_info = { 1138 .block_id = amdgpu_ras_block_to_ta(info->head.block), 1139 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), 1140 .sub_block_index = info->head.sub_block_index, 1141 .address = info->address, 1142 .value = info->value, 1143 }; 1144 int ret = -EINVAL; 1145 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, 1146 info->head.block, 1147 info->head.sub_block_index); 1148 1149 /* inject on guest isn't allowed, return success directly */ 1150 if (amdgpu_sriov_vf(adev)) 1151 return 0; 1152 1153 if (!obj) 1154 return -EINVAL; 1155 1156 if (!block_obj || !block_obj->hw_ops) { 1157 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", 1158 get_ras_block_str(&info->head)); 1159 return -EINVAL; 1160 } 1161 1162 /* Calculate XGMI relative offset */ 1163 if (adev->gmc.xgmi.num_physical_nodes > 1 && 1164 info->head.block != AMDGPU_RAS_BLOCK__GFX) { 1165 block_info.address = 1166 amdgpu_xgmi_get_relative_phy_addr(adev, 1167 block_info.address); 1168 } 1169 1170 if (block_obj->hw_ops->ras_error_inject) { 1171 if (info->head.block == AMDGPU_RAS_BLOCK__GFX) 1172 ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask); 1173 else /* Special ras_error_inject is defined (e.g: xgmi) */ 1174 ret = block_obj->hw_ops->ras_error_inject(adev, &block_info, 1175 info->instance_mask); 1176 } else { 1177 /* default path */ 1178 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask); 1179 } 1180 1181 if (ret) 1182 dev_err(adev->dev, "ras inject %s failed %d\n", 1183 get_ras_block_str(&info->head), ret); 1184 1185 return ret; 1186} 1187 1188/** 1189 * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP 1190 * @adev: pointer to AMD GPU device 1191 * @ce_count: pointer to an integer to be set to the count of correctible errors. 1192 * @ue_count: pointer to an integer to be set to the count of uncorrectible errors. 1193 * @query_info: pointer to ras_query_if 1194 * 1195 * Return 0 for query success or do nothing, otherwise return an error 1196 * on failures 1197 */ 1198static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev, 1199 unsigned long *ce_count, 1200 unsigned long *ue_count, 1201 struct ras_query_if *query_info) 1202{ 1203 int ret; 1204 1205 if (!query_info) 1206 /* do nothing if query_info is not specified */ 1207 return 0; 1208 1209 ret = amdgpu_ras_query_error_status(adev, query_info); 1210 if (ret) 1211 return ret; 1212 1213 *ce_count += query_info->ce_count; 1214 *ue_count += query_info->ue_count; 1215 1216 /* some hardware/IP supports read to clear 1217 * no need to explictly reset the err status after the query call */ 1218 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && 1219 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) { 1220 if (amdgpu_ras_reset_error_status(adev, query_info->head.block)) 1221 dev_warn(adev->dev, 1222 "Failed to reset error counter and error status\n"); 1223 } 1224 1225 return 0; 1226} 1227 1228/** 1229 * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP 1230 * @adev: pointer to AMD GPU device 1231 * @ce_count: pointer to an integer to be set to the count of correctible errors. 1232 * @ue_count: pointer to an integer to be set to the count of uncorrectible 1233 * errors. 1234 * @query_info: pointer to ras_query_if if the query request is only for 1235 * specific ip block; if info is NULL, then the qurey request is for 1236 * all the ip blocks that support query ras error counters/status 1237 * 1238 * If set, @ce_count or @ue_count, count and return the corresponding 1239 * error counts in those integer pointers. Return 0 if the device 1240 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS. 1241 */ 1242int amdgpu_ras_query_error_count(struct amdgpu_device *adev, 1243 unsigned long *ce_count, 1244 unsigned long *ue_count, 1245 struct ras_query_if *query_info) 1246{ 1247 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1248 struct ras_manager *obj; 1249 unsigned long ce, ue; 1250 int ret; 1251 1252 if (!adev->ras_enabled || !con) 1253 return -EOPNOTSUPP; 1254 1255 /* Don't count since no reporting. 1256 */ 1257 if (!ce_count && !ue_count) 1258 return 0; 1259 1260 ce = 0; 1261 ue = 0; 1262 if (!query_info) { 1263 /* query all the ip blocks that support ras query interface */ 1264 list_for_each_entry(obj, &con->head, node) { 1265 struct ras_query_if info = { 1266 .head = obj->head, 1267 }; 1268 1269 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info); 1270 } 1271 } else { 1272 /* query specific ip block */ 1273 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info); 1274 } 1275 1276 if (ret) 1277 return ret; 1278 1279 if (ce_count) 1280 *ce_count = ce; 1281 1282 if (ue_count) 1283 *ue_count = ue; 1284 1285 return 0; 1286} 1287/* query/inject/cure end */ 1288 1289#ifdef __linux__ 1290 1291/* sysfs begin */ 1292 1293static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, 1294 struct ras_badpage **bps, unsigned int *count); 1295 1296static char *amdgpu_ras_badpage_flags_str(unsigned int flags) 1297{ 1298 switch (flags) { 1299 case AMDGPU_RAS_RETIRE_PAGE_RESERVED: 1300 return "R"; 1301 case AMDGPU_RAS_RETIRE_PAGE_PENDING: 1302 return "P"; 1303 case AMDGPU_RAS_RETIRE_PAGE_FAULT: 1304 default: 1305 return "F"; 1306 } 1307} 1308 1309/** 1310 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface 1311 * 1312 * It allows user to read the bad pages of vram on the gpu through 1313 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages 1314 * 1315 * It outputs multiple lines, and each line stands for one gpu page. 1316 * 1317 * The format of one line is below, 1318 * gpu pfn : gpu page size : flags 1319 * 1320 * gpu pfn and gpu page size are printed in hex format. 1321 * flags can be one of below character, 1322 * 1323 * R: reserved, this gpu page is reserved and not able to use. 1324 * 1325 * P: pending for reserve, this gpu page is marked as bad, will be reserved 1326 * in next window of page_reserve. 1327 * 1328 * F: unable to reserve. this gpu page can't be reserved due to some reasons. 1329 * 1330 * Examples: 1331 * 1332 * .. code-block:: bash 1333 * 1334 * 0x00000001 : 0x00001000 : R 1335 * 0x00000002 : 0x00001000 : P 1336 * 1337 */ 1338 1339static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, 1340 struct kobject *kobj, struct bin_attribute *attr, 1341 char *buf, loff_t ppos, size_t count) 1342{ 1343 struct amdgpu_ras *con = 1344 container_of(attr, struct amdgpu_ras, badpages_attr); 1345 struct amdgpu_device *adev = con->adev; 1346 const unsigned int element_size = 1347 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; 1348 unsigned int start = div64_ul(ppos + element_size - 1, element_size); 1349 unsigned int end = div64_ul(ppos + count - 1, element_size); 1350 ssize_t s = 0; 1351 struct ras_badpage *bps = NULL; 1352 unsigned int bps_count = 0; 1353 1354 memset(buf, 0, count); 1355 1356 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) 1357 return 0; 1358 1359 for (; start < end && start < bps_count; start++) 1360 s += scnprintf(&buf[s], element_size + 1, 1361 "0x%08x : 0x%08x : %1s\n", 1362 bps[start].bp, 1363 bps[start].size, 1364 amdgpu_ras_badpage_flags_str(bps[start].flags)); 1365 1366 kfree(bps); 1367 1368 return s; 1369} 1370 1371static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, 1372 struct device_attribute *attr, char *buf) 1373{ 1374 struct amdgpu_ras *con = 1375 container_of(attr, struct amdgpu_ras, features_attr); 1376 1377 return sysfs_emit(buf, "feature mask: 0x%x\n", con->features); 1378} 1379 1380static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) 1381{ 1382 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1383 1384 if (adev->dev->kobj.sd) 1385 sysfs_remove_file_from_group(&adev->dev->kobj, 1386 &con->badpages_attr.attr, 1387 RAS_FS_NAME); 1388} 1389 1390static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) 1391{ 1392 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1393 struct attribute *attrs[] = { 1394 &con->features_attr.attr, 1395 NULL 1396 }; 1397 struct attribute_group group = { 1398 .name = RAS_FS_NAME, 1399 .attrs = attrs, 1400 }; 1401 1402 if (adev->dev->kobj.sd) 1403 sysfs_remove_group(&adev->dev->kobj, &group); 1404 1405 return 0; 1406} 1407 1408#endif /* __linux__ */ 1409 1410int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, 1411 struct ras_common_if *head) 1412{ 1413 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); 1414 1415 if (!obj || obj->attr_inuse) 1416 return -EINVAL; 1417 1418 STUB(); 1419 return -ENOSYS; 1420#ifdef notyet 1421 get_obj(obj); 1422 1423 snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name), 1424 "%s_err_count", head->name); 1425 1426 obj->sysfs_attr = (struct device_attribute){ 1427 .attr = { 1428 .name = obj->fs_data.sysfs_name, 1429 .mode = S_IRUGO, 1430 }, 1431 .show = amdgpu_ras_sysfs_read, 1432 }; 1433 sysfs_attr_init(&obj->sysfs_attr.attr); 1434 1435 if (sysfs_add_file_to_group(&adev->dev->kobj, 1436 &obj->sysfs_attr.attr, 1437 RAS_FS_NAME)) { 1438 put_obj(obj); 1439 return -EINVAL; 1440 } 1441 1442 obj->attr_inuse = 1; 1443 1444 return 0; 1445#endif 1446} 1447 1448int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, 1449 struct ras_common_if *head) 1450{ 1451 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); 1452 1453 if (!obj || !obj->attr_inuse) 1454 return -EINVAL; 1455 1456#ifdef __linux__ 1457 if (adev->dev->kobj.sd) 1458 sysfs_remove_file_from_group(&adev->dev->kobj, 1459 &obj->sysfs_attr.attr, 1460 RAS_FS_NAME); 1461#endif 1462 obj->attr_inuse = 0; 1463 put_obj(obj); 1464 1465 return 0; 1466} 1467 1468#ifdef __linux__ 1469 1470static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) 1471{ 1472 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1473 struct ras_manager *obj, *tmp; 1474 1475 list_for_each_entry_safe(obj, tmp, &con->head, node) { 1476 amdgpu_ras_sysfs_remove(adev, &obj->head); 1477 } 1478 1479 if (amdgpu_bad_page_threshold != 0) 1480 amdgpu_ras_sysfs_remove_bad_page_node(adev); 1481 1482 amdgpu_ras_sysfs_remove_feature_node(adev); 1483 1484 return 0; 1485} 1486/* sysfs end */ 1487 1488/** 1489 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors 1490 * 1491 * Normally when there is an uncorrectable error, the driver will reset 1492 * the GPU to recover. However, in the event of an unrecoverable error, 1493 * the driver provides an interface to reboot the system automatically 1494 * in that event. 1495 * 1496 * The following file in debugfs provides that interface: 1497 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot 1498 * 1499 * Usage: 1500 * 1501 * .. code-block:: bash 1502 * 1503 * echo true > .../ras/auto_reboot 1504 * 1505 */ 1506/* debugfs begin */ 1507static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) 1508{ 1509 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1510 struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control; 1511 struct drm_minor *minor = adev_to_drm(adev)->primary; 1512 struct dentry *dir; 1513 1514 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); 1515 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, 1516 &amdgpu_ras_debugfs_ctrl_ops); 1517 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, 1518 &amdgpu_ras_debugfs_eeprom_ops); 1519 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir, 1520 &con->bad_page_cnt_threshold); 1521 debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs); 1522 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled); 1523 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled); 1524 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev, 1525 &amdgpu_ras_debugfs_eeprom_size_ops); 1526 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table", 1527 S_IRUGO, dir, adev, 1528 &amdgpu_ras_debugfs_eeprom_table_ops); 1529 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control); 1530 1531 /* 1532 * After one uncorrectable error happens, usually GPU recovery will 1533 * be scheduled. But due to the known problem in GPU recovery failing 1534 * to bring GPU back, below interface provides one direct way to 1535 * user to reboot system automatically in such case within 1536 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine 1537 * will never be called. 1538 */ 1539 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); 1540 1541 /* 1542 * User could set this not to clean up hardware's error count register 1543 * of RAS IPs during ras recovery. 1544 */ 1545 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, 1546 &con->disable_ras_err_cnt_harvest); 1547 return dir; 1548} 1549 1550static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, 1551 struct ras_fs_if *head, 1552 struct dentry *dir) 1553{ 1554 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); 1555 1556 if (!obj || !dir) 1557 return; 1558 1559 get_obj(obj); 1560 1561 memcpy(obj->fs_data.debugfs_name, 1562 head->debugfs_name, 1563 sizeof(obj->fs_data.debugfs_name)); 1564 1565 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, 1566 obj, &amdgpu_ras_debugfs_ops); 1567} 1568 1569void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) 1570{ 1571 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1572 struct dentry *dir; 1573 struct ras_manager *obj; 1574 struct ras_fs_if fs_info; 1575 1576 /* 1577 * it won't be called in resume path, no need to check 1578 * suspend and gpu reset status 1579 */ 1580 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) 1581 return; 1582 1583 dir = amdgpu_ras_debugfs_create_ctrl_node(adev); 1584 1585 list_for_each_entry(obj, &con->head, node) { 1586 if (amdgpu_ras_is_supported(adev, obj->head.block) && 1587 (obj->attr_inuse == 1)) { 1588 snprintf(fs_info.debugfs_name, sizeof(fs_info.debugfs_name), "%s_err_inject", 1589 get_ras_block_str(&obj->head)); 1590 fs_info.head = obj->head; 1591 amdgpu_ras_debugfs_create(adev, &fs_info, dir); 1592 } 1593 } 1594} 1595 1596/* debugfs end */ 1597 1598/* ras fs */ 1599static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, 1600 amdgpu_ras_sysfs_badpages_read, NULL, 0); 1601#endif /* __linux__ */ 1602static DEVICE_ATTR(features, S_IRUGO, 1603 amdgpu_ras_sysfs_features_read, NULL); 1604static int amdgpu_ras_fs_init(struct amdgpu_device *adev) 1605{ 1606#ifdef __linux__ 1607 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1608 struct attribute_group group = { 1609 .name = RAS_FS_NAME, 1610 }; 1611 struct attribute *attrs[] = { 1612 &con->features_attr.attr, 1613 NULL 1614 }; 1615 struct bin_attribute *bin_attrs[] = { 1616 NULL, 1617 NULL, 1618 }; 1619 int r; 1620 1621 /* add features entry */ 1622 con->features_attr = dev_attr_features; 1623 group.attrs = attrs; 1624 sysfs_attr_init(attrs[0]); 1625 1626 if (amdgpu_bad_page_threshold != 0) { 1627 /* add bad_page_features entry */ 1628 bin_attr_gpu_vram_bad_pages.private = NULL; 1629 con->badpages_attr = bin_attr_gpu_vram_bad_pages; 1630 bin_attrs[0] = &con->badpages_attr; 1631 group.bin_attrs = bin_attrs; 1632 sysfs_bin_attr_init(bin_attrs[0]); 1633 } 1634 1635 r = sysfs_create_group(&adev->dev->kobj, &group); 1636 if (r) 1637 dev_err(adev->dev, "Failed to create RAS sysfs group!"); 1638#endif 1639 1640 return 0; 1641} 1642 1643static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) 1644{ 1645#ifdef __linux__ 1646 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1647 struct ras_manager *con_obj, *ip_obj, *tmp; 1648 1649 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1650 list_for_each_entry_safe(con_obj, tmp, &con->head, node) { 1651 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); 1652 if (ip_obj) 1653 put_obj(ip_obj); 1654 } 1655 } 1656 1657 amdgpu_ras_sysfs_remove_all(adev); 1658#endif 1659 return 0; 1660} 1661/* ras fs end */ 1662 1663/* ih begin */ 1664 1665/* For the hardware that cannot enable bif ring for both ras_controller_irq 1666 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status 1667 * register to check whether the interrupt is triggered or not, and properly 1668 * ack the interrupt if it is there 1669 */ 1670void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev) 1671{ 1672 /* Fatal error events are handled on host side */ 1673 if (amdgpu_sriov_vf(adev)) 1674 return; 1675 1676 if (adev->nbio.ras && 1677 adev->nbio.ras->handle_ras_controller_intr_no_bifring) 1678 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev); 1679 1680 if (adev->nbio.ras && 1681 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring) 1682 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev); 1683} 1684 1685static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj, 1686 struct amdgpu_iv_entry *entry) 1687{ 1688 bool poison_stat = false; 1689 struct amdgpu_device *adev = obj->adev; 1690 struct amdgpu_ras_block_object *block_obj = 1691 amdgpu_ras_get_ras_block(adev, obj->head.block, 0); 1692 1693 if (!block_obj) 1694 return; 1695 1696 /* both query_poison_status and handle_poison_consumption are optional, 1697 * but at least one of them should be implemented if we need poison 1698 * consumption handler 1699 */ 1700 if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) { 1701 poison_stat = block_obj->hw_ops->query_poison_status(adev); 1702 if (!poison_stat) { 1703 /* Not poison consumption interrupt, no need to handle it */ 1704 dev_info(adev->dev, "No RAS poison status in %s poison IH.\n", 1705 block_obj->ras_comm.name); 1706 1707 return; 1708 } 1709 } 1710 1711 amdgpu_umc_poison_handler(adev, false); 1712 1713 if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption) 1714 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev); 1715 1716 /* gpu reset is fallback for failed and default cases */ 1717 if (poison_stat) { 1718 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n", 1719 block_obj->ras_comm.name); 1720 amdgpu_ras_reset_gpu(adev); 1721 } else { 1722 amdgpu_gfx_poison_consumption_handler(adev, entry); 1723 } 1724} 1725 1726static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj, 1727 struct amdgpu_iv_entry *entry) 1728{ 1729 dev_info(obj->adev->dev, 1730 "Poison is created, no user action is needed.\n"); 1731} 1732 1733static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj, 1734 struct amdgpu_iv_entry *entry) 1735{ 1736 struct ras_ih_data *data = &obj->ih_data; 1737 struct ras_err_data err_data = {0, 0, 0, NULL}; 1738 int ret; 1739 1740 if (!data->cb) 1741 return; 1742 1743 /* Let IP handle its data, maybe we need get the output 1744 * from the callback to update the error type/count, etc 1745 */ 1746 ret = data->cb(obj->adev, &err_data, entry); 1747 /* ue will trigger an interrupt, and in that case 1748 * we need do a reset to recovery the whole system. 1749 * But leave IP do that recovery, here we just dispatch 1750 * the error. 1751 */ 1752 if (ret == AMDGPU_RAS_SUCCESS) { 1753 /* these counts could be left as 0 if 1754 * some blocks do not count error number 1755 */ 1756 obj->err_data.ue_count += err_data.ue_count; 1757 obj->err_data.ce_count += err_data.ce_count; 1758 } 1759} 1760 1761static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) 1762{ 1763 struct ras_ih_data *data = &obj->ih_data; 1764 struct amdgpu_iv_entry entry; 1765 1766 while (data->rptr != data->wptr) { 1767 rmb(); 1768 memcpy(&entry, &data->ring[data->rptr], 1769 data->element_size); 1770 1771 wmb(); 1772 data->rptr = (data->aligned_element_size + 1773 data->rptr) % data->ring_size; 1774 1775 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) { 1776 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC) 1777 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry); 1778 else 1779 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry); 1780 } else { 1781 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC) 1782 amdgpu_ras_interrupt_umc_handler(obj, &entry); 1783 else 1784 dev_warn(obj->adev->dev, 1785 "No RAS interrupt handler for non-UMC block with poison disabled.\n"); 1786 } 1787 } 1788} 1789 1790static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) 1791{ 1792 struct ras_ih_data *data = 1793 container_of(work, struct ras_ih_data, ih_work); 1794 struct ras_manager *obj = 1795 container_of(data, struct ras_manager, ih_data); 1796 1797 amdgpu_ras_interrupt_handler(obj); 1798} 1799 1800int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, 1801 struct ras_dispatch_if *info) 1802{ 1803 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); 1804 struct ras_ih_data *data = &obj->ih_data; 1805 1806 if (!obj) 1807 return -EINVAL; 1808 1809 if (data->inuse == 0) 1810 return 0; 1811 1812 /* Might be overflow... */ 1813 memcpy(&data->ring[data->wptr], info->entry, 1814 data->element_size); 1815 1816 wmb(); 1817 data->wptr = (data->aligned_element_size + 1818 data->wptr) % data->ring_size; 1819 1820 schedule_work(&data->ih_work); 1821 1822 return 0; 1823} 1824 1825int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, 1826 struct ras_common_if *head) 1827{ 1828 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); 1829 struct ras_ih_data *data; 1830 1831 if (!obj) 1832 return -EINVAL; 1833 1834 data = &obj->ih_data; 1835 if (data->inuse == 0) 1836 return 0; 1837 1838 cancel_work_sync(&data->ih_work); 1839 1840 kfree(data->ring); 1841 memset(data, 0, sizeof(*data)); 1842 put_obj(obj); 1843 1844 return 0; 1845} 1846 1847int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, 1848 struct ras_common_if *head) 1849{ 1850 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); 1851 struct ras_ih_data *data; 1852 struct amdgpu_ras_block_object *ras_obj; 1853 1854 if (!obj) { 1855 /* in case we registe the IH before enable ras feature */ 1856 obj = amdgpu_ras_create_obj(adev, head); 1857 if (!obj) 1858 return -EINVAL; 1859 } else 1860 get_obj(obj); 1861 1862 ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm); 1863 1864 data = &obj->ih_data; 1865 /* add the callback.etc */ 1866 *data = (struct ras_ih_data) { 1867 .inuse = 0, 1868 .cb = ras_obj->ras_cb, 1869 .element_size = sizeof(struct amdgpu_iv_entry), 1870 .rptr = 0, 1871 .wptr = 0, 1872 }; 1873 1874 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); 1875 1876 data->aligned_element_size = ALIGN(data->element_size, 8); 1877 /* the ring can store 64 iv entries. */ 1878 data->ring_size = 64 * data->aligned_element_size; 1879 data->ring = kmalloc(data->ring_size, GFP_KERNEL); 1880 if (!data->ring) { 1881 put_obj(obj); 1882 return -ENOMEM; 1883 } 1884 1885 /* IH is ready */ 1886 data->inuse = 1; 1887 1888 return 0; 1889} 1890 1891static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) 1892{ 1893 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1894 struct ras_manager *obj, *tmp; 1895 1896 list_for_each_entry_safe(obj, tmp, &con->head, node) { 1897 amdgpu_ras_interrupt_remove_handler(adev, &obj->head); 1898 } 1899 1900 return 0; 1901} 1902/* ih end */ 1903 1904/* traversal all IPs except NBIO to query error counter */ 1905static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) 1906{ 1907 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1908 struct ras_manager *obj; 1909 1910 if (!adev->ras_enabled || !con) 1911 return; 1912 1913 list_for_each_entry(obj, &con->head, node) { 1914 struct ras_query_if info = { 1915 .head = obj->head, 1916 }; 1917 1918 /* 1919 * PCIE_BIF IP has one different isr by ras controller 1920 * interrupt, the specific ras counter query will be 1921 * done in that isr. So skip such block from common 1922 * sync flood interrupt isr calling. 1923 */ 1924 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) 1925 continue; 1926 1927 /* 1928 * this is a workaround for aldebaran, skip send msg to 1929 * smu to get ecc_info table due to smu handle get ecc 1930 * info table failed temporarily. 1931 * should be removed until smu fix handle ecc_info table. 1932 */ 1933 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) && 1934 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2))) 1935 continue; 1936 1937 amdgpu_ras_query_error_status(adev, &info); 1938 1939 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && 1940 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) && 1941 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) { 1942 if (amdgpu_ras_reset_error_status(adev, info.head.block)) 1943 dev_warn(adev->dev, "Failed to reset error counter and error status"); 1944 } 1945 } 1946} 1947 1948/* Parse RdRspStatus and WrRspStatus */ 1949static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, 1950 struct ras_query_if *info) 1951{ 1952 struct amdgpu_ras_block_object *block_obj; 1953 /* 1954 * Only two block need to query read/write 1955 * RspStatus at current state 1956 */ 1957 if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) && 1958 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB)) 1959 return; 1960 1961 block_obj = amdgpu_ras_get_ras_block(adev, 1962 info->head.block, 1963 info->head.sub_block_index); 1964 1965 if (!block_obj || !block_obj->hw_ops) { 1966 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", 1967 get_ras_block_str(&info->head)); 1968 return; 1969 } 1970 1971 if (block_obj->hw_ops->query_ras_error_status) 1972 block_obj->hw_ops->query_ras_error_status(adev); 1973 1974} 1975 1976static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) 1977{ 1978 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 1979 struct ras_manager *obj; 1980 1981 if (!adev->ras_enabled || !con) 1982 return; 1983 1984 list_for_each_entry(obj, &con->head, node) { 1985 struct ras_query_if info = { 1986 .head = obj->head, 1987 }; 1988 1989 amdgpu_ras_error_status_query(adev, &info); 1990 } 1991} 1992 1993/* recovery begin */ 1994 1995/* return 0 on success. 1996 * caller need free bps. 1997 */ 1998static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, 1999 struct ras_badpage **bps, unsigned int *count) 2000{ 2001 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2002 struct ras_err_handler_data *data; 2003 int i = 0; 2004 int ret = 0, status; 2005 2006 if (!con || !con->eh_data || !bps || !count) 2007 return -EINVAL; 2008 2009 mutex_lock(&con->recovery_lock); 2010 data = con->eh_data; 2011 if (!data || data->count == 0) { 2012 *bps = NULL; 2013 ret = -EINVAL; 2014 goto out; 2015 } 2016 2017 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); 2018 if (!*bps) { 2019 ret = -ENOMEM; 2020 goto out; 2021 } 2022 2023 for (; i < data->count; i++) { 2024 (*bps)[i] = (struct ras_badpage){ 2025 .bp = data->bps[i].retired_page, 2026 .size = AMDGPU_GPU_PAGE_SIZE, 2027 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, 2028 }; 2029 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr, 2030 data->bps[i].retired_page); 2031 if (status == -EBUSY) 2032 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; 2033 else if (status == -ENOENT) 2034 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; 2035 } 2036 2037 *count = data->count; 2038out: 2039 mutex_unlock(&con->recovery_lock); 2040 return ret; 2041} 2042 2043static void amdgpu_ras_do_recovery(struct work_struct *work) 2044{ 2045 struct amdgpu_ras *ras = 2046 container_of(work, struct amdgpu_ras, recovery_work); 2047 struct amdgpu_device *remote_adev = NULL; 2048 struct amdgpu_device *adev = ras->adev; 2049 struct list_head device_list, *device_list_handle = NULL; 2050 2051 if (!ras->disable_ras_err_cnt_harvest) { 2052 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); 2053 2054 /* Build list of devices to query RAS related errors */ 2055 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { 2056 device_list_handle = &hive->device_list; 2057 } else { 2058 INIT_LIST_HEAD(&device_list); 2059 list_add_tail(&adev->gmc.xgmi.head, &device_list); 2060 device_list_handle = &device_list; 2061 } 2062 2063 list_for_each_entry(remote_adev, 2064 device_list_handle, gmc.xgmi.head) { 2065 amdgpu_ras_query_err_status(remote_adev); 2066 amdgpu_ras_log_on_err_counter(remote_adev); 2067 } 2068 2069 amdgpu_put_xgmi_hive(hive); 2070 } 2071 2072 if (amdgpu_device_should_recover_gpu(ras->adev)) { 2073 struct amdgpu_reset_context reset_context; 2074 memset(&reset_context, 0, sizeof(reset_context)); 2075 2076 reset_context.method = AMD_RESET_METHOD_NONE; 2077 reset_context.reset_req_dev = adev; 2078 2079 /* Perform full reset in fatal error mode */ 2080 if (!amdgpu_ras_is_poison_mode_supported(ras->adev)) 2081 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2082 else { 2083 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2084 2085 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) { 2086 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET; 2087 reset_context.method = AMD_RESET_METHOD_MODE2; 2088 } 2089 2090 /* Fatal error occurs in poison mode, mode1 reset is used to 2091 * recover gpu. 2092 */ 2093 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) { 2094 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET; 2095 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2096 2097 psp_fatal_error_recovery_quirk(&adev->psp); 2098 } 2099 } 2100 2101 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context); 2102 } 2103 atomic_set(&ras->in_recovery, 0); 2104} 2105 2106/* alloc/realloc bps array */ 2107static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, 2108 struct ras_err_handler_data *data, int pages) 2109{ 2110 unsigned int old_space = data->count + data->space_left; 2111 unsigned int new_space = old_space + pages; 2112 unsigned int align_space = ALIGN(new_space, 512); 2113 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); 2114 2115 if (!bps) { 2116 return -ENOMEM; 2117 } 2118 2119 if (data->bps) { 2120 memcpy(bps, data->bps, 2121 data->count * sizeof(*data->bps)); 2122 kfree(data->bps); 2123 } 2124 2125 data->bps = bps; 2126 data->space_left += align_space - old_space; 2127 return 0; 2128} 2129 2130/* it deal with vram only. */ 2131int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, 2132 struct eeprom_table_record *bps, int pages) 2133{ 2134 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2135 struct ras_err_handler_data *data; 2136 int ret = 0; 2137 uint32_t i; 2138 2139 if (!con || !con->eh_data || !bps || pages <= 0) 2140 return 0; 2141 2142 mutex_lock(&con->recovery_lock); 2143 data = con->eh_data; 2144 if (!data) 2145 goto out; 2146 2147 for (i = 0; i < pages; i++) { 2148 if (amdgpu_ras_check_bad_page_unlock(con, 2149 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) 2150 continue; 2151 2152 if (!data->space_left && 2153 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { 2154 ret = -ENOMEM; 2155 goto out; 2156 } 2157 2158 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, 2159 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, 2160 AMDGPU_GPU_PAGE_SIZE); 2161 2162 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); 2163 data->count++; 2164 data->space_left--; 2165 } 2166out: 2167 mutex_unlock(&con->recovery_lock); 2168 2169 return ret; 2170} 2171 2172/* 2173 * write error record array to eeprom, the function should be 2174 * protected by recovery_lock 2175 * new_cnt: new added UE count, excluding reserved bad pages, can be NULL 2176 */ 2177int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, 2178 unsigned long *new_cnt) 2179{ 2180 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2181 struct ras_err_handler_data *data; 2182 struct amdgpu_ras_eeprom_control *control; 2183 int save_count; 2184 2185 if (!con || !con->eh_data) { 2186 if (new_cnt) 2187 *new_cnt = 0; 2188 2189 return 0; 2190 } 2191 2192 mutex_lock(&con->recovery_lock); 2193 control = &con->eeprom_control; 2194 data = con->eh_data; 2195 save_count = data->count - control->ras_num_recs; 2196 mutex_unlock(&con->recovery_lock); 2197 2198 if (new_cnt) 2199 *new_cnt = save_count / adev->umc.retire_unit; 2200 2201 /* only new entries are saved */ 2202 if (save_count > 0) { 2203 if (amdgpu_ras_eeprom_append(control, 2204 &data->bps[control->ras_num_recs], 2205 save_count)) { 2206 dev_err(adev->dev, "Failed to save EEPROM table data!"); 2207 return -EIO; 2208 } 2209 2210 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); 2211 } 2212 2213 return 0; 2214} 2215 2216/* 2217 * read error record array in eeprom and reserve enough space for 2218 * storing new bad pages 2219 */ 2220static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) 2221{ 2222 struct amdgpu_ras_eeprom_control *control = 2223 &adev->psp.ras_context.ras->eeprom_control; 2224 struct eeprom_table_record *bps; 2225 int ret; 2226 2227 /* no bad page record, skip eeprom access */ 2228 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0) 2229 return 0; 2230 2231 bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL); 2232 if (!bps) 2233 return -ENOMEM; 2234 2235 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs); 2236 if (ret) 2237 dev_err(adev->dev, "Failed to load EEPROM table records!"); 2238 else 2239 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs); 2240 2241 kfree(bps); 2242 return ret; 2243} 2244 2245static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, 2246 uint64_t addr) 2247{ 2248 struct ras_err_handler_data *data = con->eh_data; 2249 int i; 2250 2251 addr >>= AMDGPU_GPU_PAGE_SHIFT; 2252 for (i = 0; i < data->count; i++) 2253 if (addr == data->bps[i].retired_page) 2254 return true; 2255 2256 return false; 2257} 2258 2259/* 2260 * check if an address belongs to bad page 2261 * 2262 * Note: this check is only for umc block 2263 */ 2264static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, 2265 uint64_t addr) 2266{ 2267 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2268 bool ret = false; 2269 2270 if (!con || !con->eh_data) 2271 return ret; 2272 2273 mutex_lock(&con->recovery_lock); 2274 ret = amdgpu_ras_check_bad_page_unlock(con, addr); 2275 mutex_unlock(&con->recovery_lock); 2276 return ret; 2277} 2278 2279static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, 2280 uint32_t max_count) 2281{ 2282 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2283 2284 /* 2285 * Justification of value bad_page_cnt_threshold in ras structure 2286 * 2287 * Generally, 0 <= amdgpu_bad_page_threshold <= max record length 2288 * in eeprom or amdgpu_bad_page_threshold == -2, introduce two 2289 * scenarios accordingly. 2290 * 2291 * Bad page retirement enablement: 2292 * - If amdgpu_bad_page_threshold = -2, 2293 * bad_page_cnt_threshold = typical value by formula. 2294 * 2295 * - When the value from user is 0 < amdgpu_bad_page_threshold < 2296 * max record length in eeprom, use it directly. 2297 * 2298 * Bad page retirement disablement: 2299 * - If amdgpu_bad_page_threshold = 0, bad page retirement 2300 * functionality is disabled, and bad_page_cnt_threshold will 2301 * take no effect. 2302 */ 2303 2304 if (amdgpu_bad_page_threshold < 0) { 2305 u64 val = adev->gmc.mc_vram_size; 2306 2307 do_div(val, RAS_BAD_PAGE_COVER); 2308 con->bad_page_cnt_threshold = min(lower_32_bits(val), 2309 max_count); 2310 } else { 2311 con->bad_page_cnt_threshold = min_t(int, max_count, 2312 amdgpu_bad_page_threshold); 2313 } 2314} 2315 2316int amdgpu_ras_recovery_init(struct amdgpu_device *adev) 2317{ 2318 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2319 struct ras_err_handler_data **data; 2320 u32 max_eeprom_records_count = 0; 2321 bool exc_err_limit = false; 2322 int ret; 2323 2324 if (!con || amdgpu_sriov_vf(adev)) 2325 return 0; 2326 2327 /* Allow access to RAS EEPROM via debugfs, when the ASIC 2328 * supports RAS and debugfs is enabled, but when 2329 * adev->ras_enabled is unset, i.e. when "ras_enable" 2330 * module parameter is set to 0. 2331 */ 2332 con->adev = adev; 2333 2334 if (!adev->ras_enabled) 2335 return 0; 2336 2337 data = &con->eh_data; 2338 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); 2339 if (!*data) { 2340 ret = -ENOMEM; 2341 goto out; 2342 } 2343 2344 rw_init(&con->recovery_lock, "rasrec"); 2345 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); 2346 atomic_set(&con->in_recovery, 0); 2347 con->eeprom_control.bad_channel_bitmap = 0; 2348 2349 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control); 2350 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count); 2351 2352 /* Todo: During test the SMU might fail to read the eeprom through I2C 2353 * when the GPU is pending on XGMI reset during probe time 2354 * (Mostly after second bus reset), skip it now 2355 */ 2356 if (adev->gmc.xgmi.pending_reset) 2357 return 0; 2358 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); 2359 /* 2360 * This calling fails when exc_err_limit is true or 2361 * ret != 0. 2362 */ 2363 if (exc_err_limit || ret) 2364 goto free; 2365 2366 if (con->eeprom_control.ras_num_recs) { 2367 ret = amdgpu_ras_load_bad_pages(adev); 2368 if (ret) 2369 goto free; 2370 2371 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs); 2372 2373 if (con->update_channel_flag == true) { 2374 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap); 2375 con->update_channel_flag = false; 2376 } 2377 } 2378 2379#ifdef CONFIG_X86_MCE_AMD 2380 if ((adev->asic_type == CHIP_ALDEBARAN) && 2381 (adev->gmc.xgmi.connected_to_cpu)) 2382 amdgpu_register_bad_pages_mca_notifier(adev); 2383#endif 2384 return 0; 2385 2386free: 2387 kfree((*data)->bps); 2388 kfree(*data); 2389 con->eh_data = NULL; 2390out: 2391 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret); 2392 2393 /* 2394 * Except error threshold exceeding case, other failure cases in this 2395 * function would not fail amdgpu driver init. 2396 */ 2397 if (!exc_err_limit) 2398 ret = 0; 2399 else 2400 ret = -EINVAL; 2401 2402 return ret; 2403} 2404 2405static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) 2406{ 2407 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2408 struct ras_err_handler_data *data = con->eh_data; 2409 2410 /* recovery_init failed to init it, fini is useless */ 2411 if (!data) 2412 return 0; 2413 2414 cancel_work_sync(&con->recovery_work); 2415 2416 mutex_lock(&con->recovery_lock); 2417 con->eh_data = NULL; 2418 kfree(data->bps); 2419 kfree(data); 2420 mutex_unlock(&con->recovery_lock); 2421 2422 return 0; 2423} 2424/* recovery end */ 2425 2426static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) 2427{ 2428 if (amdgpu_sriov_vf(adev)) { 2429 switch (adev->ip_versions[MP0_HWIP][0]) { 2430 case IP_VERSION(13, 0, 2): 2431 case IP_VERSION(13, 0, 6): 2432 return true; 2433 default: 2434 return false; 2435 } 2436 } 2437 2438 if (adev->asic_type == CHIP_IP_DISCOVERY) { 2439 switch (adev->ip_versions[MP0_HWIP][0]) { 2440 case IP_VERSION(13, 0, 0): 2441 case IP_VERSION(13, 0, 6): 2442 case IP_VERSION(13, 0, 10): 2443 return true; 2444 default: 2445 return false; 2446 } 2447 } 2448 2449 return adev->asic_type == CHIP_VEGA10 || 2450 adev->asic_type == CHIP_VEGA20 || 2451 adev->asic_type == CHIP_ARCTURUS || 2452 adev->asic_type == CHIP_ALDEBARAN || 2453 adev->asic_type == CHIP_SIENNA_CICHLID; 2454} 2455 2456/* 2457 * this is workaround for vega20 workstation sku, 2458 * force enable gfx ras, ignore vbios gfx ras flag 2459 * due to GC EDC can not write 2460 */ 2461static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) 2462{ 2463 struct atom_context *ctx = adev->mode_info.atom_context; 2464 2465 if (!ctx) 2466 return; 2467 2468 if (strnstr(ctx->vbios_pn, "D16406", 2469 sizeof(ctx->vbios_pn)) || 2470 strnstr(ctx->vbios_pn, "D36002", 2471 sizeof(ctx->vbios_pn))) 2472 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); 2473} 2474 2475/* 2476 * check hardware's ras ability which will be saved in hw_supported. 2477 * if hardware does not support ras, we can skip some ras initializtion and 2478 * forbid some ras operations from IP. 2479 * if software itself, say boot parameter, limit the ras ability. We still 2480 * need allow IP do some limited operations, like disable. In such case, 2481 * we have to initialize ras as normal. but need check if operation is 2482 * allowed or not in each function. 2483 */ 2484static void amdgpu_ras_check_supported(struct amdgpu_device *adev) 2485{ 2486 adev->ras_hw_enabled = adev->ras_enabled = 0; 2487 2488 if (!amdgpu_ras_asic_supported(adev)) 2489 return; 2490 2491 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { 2492 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { 2493 dev_info(adev->dev, "MEM ECC is active.\n"); 2494 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | 2495 1 << AMDGPU_RAS_BLOCK__DF); 2496 } else { 2497 dev_info(adev->dev, "MEM ECC is not presented.\n"); 2498 } 2499 2500 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { 2501 dev_info(adev->dev, "SRAM ECC is active.\n"); 2502 if (!amdgpu_sriov_vf(adev)) 2503 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | 2504 1 << AMDGPU_RAS_BLOCK__DF); 2505 else 2506 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF | 2507 1 << AMDGPU_RAS_BLOCK__SDMA | 2508 1 << AMDGPU_RAS_BLOCK__GFX); 2509 2510 /* VCN/JPEG RAS can be supported on both bare metal and 2511 * SRIOV environment 2512 */ 2513 if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0) || 2514 adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 0)) 2515 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN | 2516 1 << AMDGPU_RAS_BLOCK__JPEG); 2517 else 2518 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN | 2519 1 << AMDGPU_RAS_BLOCK__JPEG); 2520 2521 /* 2522 * XGMI RAS is not supported if xgmi num physical nodes 2523 * is zero 2524 */ 2525 if (!adev->gmc.xgmi.num_physical_nodes) 2526 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL); 2527 } else { 2528 dev_info(adev->dev, "SRAM ECC is not presented.\n"); 2529 } 2530 } else { 2531 /* driver only manages a few IP blocks RAS feature 2532 * when GPU is connected cpu through XGMI */ 2533 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | 2534 1 << AMDGPU_RAS_BLOCK__SDMA | 2535 1 << AMDGPU_RAS_BLOCK__MMHUB); 2536 } 2537 2538 amdgpu_ras_get_quirks(adev); 2539 2540 /* hw_supported needs to be aligned with RAS block mask. */ 2541 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; 2542 2543 2544 /* 2545 * Disable ras feature for aqua vanjaram 2546 * by default on apu platform. 2547 */ 2548 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6) && 2549 adev->gmc.is_app_apu) 2550 adev->ras_enabled = amdgpu_ras_enable != 1 ? 0 : 2551 adev->ras_hw_enabled & amdgpu_ras_mask; 2552 else 2553 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : 2554 adev->ras_hw_enabled & amdgpu_ras_mask; 2555} 2556 2557static void amdgpu_ras_counte_dw(struct work_struct *work) 2558{ 2559 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, 2560 ras_counte_delay_work.work); 2561 struct amdgpu_device *adev = con->adev; 2562 struct drm_device *dev = adev_to_drm(adev); 2563 unsigned long ce_count, ue_count; 2564 int res; 2565 2566 res = pm_runtime_get_sync(dev->dev); 2567 if (res < 0) 2568 goto Out; 2569 2570 /* Cache new values. 2571 */ 2572 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) { 2573 atomic_set(&con->ras_ce_count, ce_count); 2574 atomic_set(&con->ras_ue_count, ue_count); 2575 } 2576 2577 pm_runtime_mark_last_busy(dev->dev); 2578Out: 2579 pm_runtime_put_autosuspend(dev->dev); 2580} 2581 2582static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev) 2583{ 2584 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2585 bool df_poison, umc_poison; 2586 2587 /* poison setting is useless on SRIOV guest */ 2588 if (amdgpu_sriov_vf(adev) || !con) 2589 return; 2590 2591 /* Init poison supported flag, the default value is false */ 2592 if (adev->gmc.xgmi.connected_to_cpu) { 2593 /* enabled by default when GPU is connected to CPU */ 2594 con->poison_supported = true; 2595 } else if (adev->df.funcs && 2596 adev->df.funcs->query_ras_poison_mode && 2597 adev->umc.ras && 2598 adev->umc.ras->query_ras_poison_mode) { 2599 df_poison = 2600 adev->df.funcs->query_ras_poison_mode(adev); 2601 umc_poison = 2602 adev->umc.ras->query_ras_poison_mode(adev); 2603 2604 /* Only poison is set in both DF and UMC, we can support it */ 2605 if (df_poison && umc_poison) 2606 con->poison_supported = true; 2607 else if (df_poison != umc_poison) 2608 dev_warn(adev->dev, 2609 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n", 2610 df_poison, umc_poison); 2611 } 2612} 2613 2614int amdgpu_ras_init(struct amdgpu_device *adev) 2615{ 2616 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2617 int r; 2618 2619 if (con) 2620 return 0; 2621 2622 con = kmalloc(sizeof(struct amdgpu_ras) + 2623 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT + 2624 sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT, 2625 GFP_KERNEL|__GFP_ZERO); 2626 if (!con) 2627 return -ENOMEM; 2628 2629 con->adev = adev; 2630 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw); 2631 atomic_set(&con->ras_ce_count, 0); 2632 atomic_set(&con->ras_ue_count, 0); 2633 2634 con->objs = (struct ras_manager *)(con + 1); 2635 2636 amdgpu_ras_set_context(adev, con); 2637 2638 amdgpu_ras_check_supported(adev); 2639 2640 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { 2641 /* set gfx block ras context feature for VEGA20 Gaming 2642 * send ras disable cmd to ras ta during ras late init. 2643 */ 2644 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { 2645 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); 2646 2647 return 0; 2648 } 2649 2650 r = 0; 2651 goto release_con; 2652 } 2653 2654 con->update_channel_flag = false; 2655 con->features = 0; 2656 INIT_LIST_HEAD(&con->head); 2657 /* Might need get this flag from vbios. */ 2658 con->flags = RAS_DEFAULT_FLAGS; 2659 2660 /* initialize nbio ras function ahead of any other 2661 * ras functions so hardware fatal error interrupt 2662 * can be enabled as early as possible */ 2663 switch (adev->ip_versions[NBIO_HWIP][0]) { 2664 case IP_VERSION(7, 4, 0): 2665 case IP_VERSION(7, 4, 1): 2666 case IP_VERSION(7, 4, 4): 2667 if (!adev->gmc.xgmi.connected_to_cpu) 2668 adev->nbio.ras = &nbio_v7_4_ras; 2669 break; 2670 case IP_VERSION(4, 3, 0): 2671 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF)) 2672 /* unlike other generation of nbio ras, 2673 * nbio v4_3 only support fatal error interrupt 2674 * to inform software that DF is freezed due to 2675 * system fatal error event. driver should not 2676 * enable nbio ras in such case. Instead, 2677 * check DF RAS */ 2678 adev->nbio.ras = &nbio_v4_3_ras; 2679 break; 2680 case IP_VERSION(7, 9, 0): 2681 if (!adev->gmc.is_app_apu) 2682 adev->nbio.ras = &nbio_v7_9_ras; 2683 break; 2684 default: 2685 /* nbio ras is not available */ 2686 break; 2687 } 2688 2689 /* nbio ras block needs to be enabled ahead of other ras blocks 2690 * to handle fatal error */ 2691 r = amdgpu_nbio_ras_sw_init(adev); 2692 if (r) 2693 return r; 2694 2695 if (adev->nbio.ras && 2696 adev->nbio.ras->init_ras_controller_interrupt) { 2697 r = adev->nbio.ras->init_ras_controller_interrupt(adev); 2698 if (r) 2699 goto release_con; 2700 } 2701 2702 if (adev->nbio.ras && 2703 adev->nbio.ras->init_ras_err_event_athub_interrupt) { 2704 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev); 2705 if (r) 2706 goto release_con; 2707 } 2708 2709 amdgpu_ras_query_poison_mode(adev); 2710 2711 if (amdgpu_ras_fs_init(adev)) { 2712 r = -EINVAL; 2713 goto release_con; 2714 } 2715 2716 dev_info(adev->dev, "RAS INFO: ras initialized successfully, " 2717 "hardware ability[%x] ras_mask[%x]\n", 2718 adev->ras_hw_enabled, adev->ras_enabled); 2719 2720 return 0; 2721release_con: 2722 amdgpu_ras_set_context(adev, NULL); 2723 kfree(con); 2724 2725 return r; 2726} 2727 2728int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) 2729{ 2730 if (adev->gmc.xgmi.connected_to_cpu || 2731 adev->gmc.is_app_apu) 2732 return 1; 2733 return 0; 2734} 2735 2736static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, 2737 struct ras_common_if *ras_block) 2738{ 2739 struct ras_query_if info = { 2740 .head = *ras_block, 2741 }; 2742 2743 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 2744 return 0; 2745 2746 if (amdgpu_ras_query_error_status(adev, &info) != 0) 2747 DRM_WARN("RAS init harvest failure"); 2748 2749 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) 2750 DRM_WARN("RAS init harvest reset failure"); 2751 2752 return 0; 2753} 2754 2755bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev) 2756{ 2757 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2758 2759 if (!con) 2760 return false; 2761 2762 return con->poison_supported; 2763} 2764 2765/* helper function to handle common stuff in ip late init phase */ 2766int amdgpu_ras_block_late_init(struct amdgpu_device *adev, 2767 struct ras_common_if *ras_block) 2768{ 2769 struct amdgpu_ras_block_object *ras_obj = NULL; 2770 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2771 struct ras_query_if *query_info; 2772 unsigned long ue_count, ce_count; 2773 int r; 2774 2775 /* disable RAS feature per IP block if it is not supported */ 2776 if (!amdgpu_ras_is_supported(adev, ras_block->block)) { 2777 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); 2778 return 0; 2779 } 2780 2781 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); 2782 if (r) { 2783 if (adev->in_suspend || amdgpu_in_reset(adev)) { 2784 /* in resume phase, if fail to enable ras, 2785 * clean up all ras fs nodes, and disable ras */ 2786 goto cleanup; 2787 } else 2788 return r; 2789 } 2790 2791 /* check for errors on warm reset edc persisant supported ASIC */ 2792 amdgpu_persistent_edc_harvesting(adev, ras_block); 2793 2794 /* in resume phase, no need to create ras fs node */ 2795 if (adev->in_suspend || amdgpu_in_reset(adev)) 2796 return 0; 2797 2798 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); 2799 if (ras_obj->ras_cb || (ras_obj->hw_ops && 2800 (ras_obj->hw_ops->query_poison_status || 2801 ras_obj->hw_ops->handle_poison_consumption))) { 2802 r = amdgpu_ras_interrupt_add_handler(adev, ras_block); 2803 if (r) 2804 goto cleanup; 2805 } 2806 2807 if (ras_obj->hw_ops && 2808 (ras_obj->hw_ops->query_ras_error_count || 2809 ras_obj->hw_ops->query_ras_error_status)) { 2810 r = amdgpu_ras_sysfs_create(adev, ras_block); 2811 if (r) 2812 goto interrupt; 2813 2814 /* Those are the cached values at init. 2815 */ 2816 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL); 2817 if (!query_info) 2818 return -ENOMEM; 2819 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if)); 2820 2821 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) { 2822 atomic_set(&con->ras_ce_count, ce_count); 2823 atomic_set(&con->ras_ue_count, ue_count); 2824 } 2825 2826 kfree(query_info); 2827 } 2828 2829 return 0; 2830 2831interrupt: 2832 if (ras_obj->ras_cb) 2833 amdgpu_ras_interrupt_remove_handler(adev, ras_block); 2834cleanup: 2835 amdgpu_ras_feature_enable(adev, ras_block, 0); 2836 return r; 2837} 2838 2839static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev, 2840 struct ras_common_if *ras_block) 2841{ 2842 return amdgpu_ras_block_late_init(adev, ras_block); 2843} 2844 2845/* helper function to remove ras fs node and interrupt handler */ 2846void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, 2847 struct ras_common_if *ras_block) 2848{ 2849 struct amdgpu_ras_block_object *ras_obj; 2850 if (!ras_block) 2851 return; 2852 2853 amdgpu_ras_sysfs_remove(adev, ras_block); 2854 2855 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); 2856 if (ras_obj->ras_cb) 2857 amdgpu_ras_interrupt_remove_handler(adev, ras_block); 2858} 2859 2860static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev, 2861 struct ras_common_if *ras_block) 2862{ 2863 return amdgpu_ras_block_late_fini(adev, ras_block); 2864} 2865 2866/* do some init work after IP late init as dependence. 2867 * and it runs in resume/gpu reset/booting up cases. 2868 */ 2869void amdgpu_ras_resume(struct amdgpu_device *adev) 2870{ 2871 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2872 struct ras_manager *obj, *tmp; 2873 2874 if (!adev->ras_enabled || !con) { 2875 /* clean ras context for VEGA20 Gaming after send ras disable cmd */ 2876 amdgpu_release_ras_context(adev); 2877 2878 return; 2879 } 2880 2881 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { 2882 /* Set up all other IPs which are not implemented. There is a 2883 * tricky thing that IP's actual ras error type should be 2884 * MULTI_UNCORRECTABLE, but as driver does not handle it, so 2885 * ERROR_NONE make sense anyway. 2886 */ 2887 amdgpu_ras_enable_all_features(adev, 1); 2888 2889 /* We enable ras on all hw_supported block, but as boot 2890 * parameter might disable some of them and one or more IP has 2891 * not implemented yet. So we disable them on behalf. 2892 */ 2893 list_for_each_entry_safe(obj, tmp, &con->head, node) { 2894 if (!amdgpu_ras_is_supported(adev, obj->head.block)) { 2895 amdgpu_ras_feature_enable(adev, &obj->head, 0); 2896 /* there should be no any reference. */ 2897 WARN_ON(alive_obj(obj)); 2898 } 2899 } 2900 } 2901} 2902 2903void amdgpu_ras_suspend(struct amdgpu_device *adev) 2904{ 2905 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2906 2907 if (!adev->ras_enabled || !con) 2908 return; 2909 2910 amdgpu_ras_disable_all_features(adev, 0); 2911 /* Make sure all ras objects are disabled. */ 2912 if (con->features) 2913 amdgpu_ras_disable_all_features(adev, 1); 2914} 2915 2916int amdgpu_ras_late_init(struct amdgpu_device *adev) 2917{ 2918 struct amdgpu_ras_block_list *node, *tmp; 2919 struct amdgpu_ras_block_object *obj; 2920 int r; 2921 2922 /* Guest side doesn't need init ras feature */ 2923 if (amdgpu_sriov_vf(adev)) 2924 return 0; 2925 2926 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { 2927 if (!node->ras_obj) { 2928 dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); 2929 continue; 2930 } 2931 2932 obj = node->ras_obj; 2933 if (obj->ras_late_init) { 2934 r = obj->ras_late_init(adev, &obj->ras_comm); 2935 if (r) { 2936 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n", 2937 obj->ras_comm.name, r); 2938 return r; 2939 } 2940 } else 2941 amdgpu_ras_block_late_init_default(adev, &obj->ras_comm); 2942 } 2943 2944 return 0; 2945} 2946 2947/* do some fini work before IP fini as dependence */ 2948int amdgpu_ras_pre_fini(struct amdgpu_device *adev) 2949{ 2950 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2951 2952 if (!adev->ras_enabled || !con) 2953 return 0; 2954 2955 2956 /* Need disable ras on all IPs here before ip [hw/sw]fini */ 2957 if (con->features) 2958 amdgpu_ras_disable_all_features(adev, 0); 2959 amdgpu_ras_recovery_fini(adev); 2960 return 0; 2961} 2962 2963int amdgpu_ras_fini(struct amdgpu_device *adev) 2964{ 2965 struct amdgpu_ras_block_list *ras_node, *tmp; 2966 struct amdgpu_ras_block_object *obj = NULL; 2967 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 2968 2969 if (!adev->ras_enabled || !con) 2970 return 0; 2971 2972 list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) { 2973 if (ras_node->ras_obj) { 2974 obj = ras_node->ras_obj; 2975 if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) && 2976 obj->ras_fini) 2977 obj->ras_fini(adev, &obj->ras_comm); 2978 else 2979 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm); 2980 } 2981 2982 /* Clear ras blocks from ras_list and free ras block list node */ 2983 list_del(&ras_node->node); 2984 kfree(ras_node); 2985 } 2986 2987 amdgpu_ras_fs_fini(adev); 2988 amdgpu_ras_interrupt_remove_all(adev); 2989 2990 WARN(con->features, "Feature mask is not cleared"); 2991 2992 if (con->features) 2993 amdgpu_ras_disable_all_features(adev, 1); 2994 2995 cancel_delayed_work_sync(&con->ras_counte_delay_work); 2996 2997 amdgpu_ras_set_context(adev, NULL); 2998 kfree(con); 2999 3000 return 0; 3001} 3002 3003void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) 3004{ 3005 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { 3006 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 3007 3008 dev_info(adev->dev, "uncorrectable hardware error" 3009 "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); 3010 3011 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET; 3012 amdgpu_ras_reset_gpu(adev); 3013 } 3014} 3015 3016bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) 3017{ 3018 if (adev->asic_type == CHIP_VEGA20 && 3019 adev->pm.fw_version <= 0x283400) { 3020 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && 3021 amdgpu_ras_intr_triggered(); 3022 } 3023 3024 return false; 3025} 3026 3027void amdgpu_release_ras_context(struct amdgpu_device *adev) 3028{ 3029 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 3030 3031 if (!con) 3032 return; 3033 3034 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { 3035 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); 3036 amdgpu_ras_set_context(adev, NULL); 3037 kfree(con); 3038 } 3039} 3040 3041#ifdef CONFIG_X86_MCE_AMD 3042static struct amdgpu_device *find_adev(uint32_t node_id) 3043{ 3044 int i; 3045 struct amdgpu_device *adev = NULL; 3046 3047 for (i = 0; i < mce_adev_list.num_gpu; i++) { 3048 adev = mce_adev_list.devs[i]; 3049 3050 if (adev && adev->gmc.xgmi.connected_to_cpu && 3051 adev->gmc.xgmi.physical_node_id == node_id) 3052 break; 3053 adev = NULL; 3054 } 3055 3056 return adev; 3057} 3058 3059#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) 3060#define GET_UMC_INST(m) (((m) >> 21) & 0x7) 3061#define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4)) 3062#define GPU_ID_OFFSET 8 3063 3064static int amdgpu_bad_page_notifier(struct notifier_block *nb, 3065 unsigned long val, void *data) 3066{ 3067 struct mce *m = (struct mce *)data; 3068 struct amdgpu_device *adev = NULL; 3069 uint32_t gpu_id = 0; 3070 uint32_t umc_inst = 0, ch_inst = 0; 3071 3072 /* 3073 * If the error was generated in UMC_V2, which belongs to GPU UMCs, 3074 * and error occurred in DramECC (Extended error code = 0) then only 3075 * process the error, else bail out. 3076 */ 3077 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && 3078 (XEC(m->status, 0x3f) == 0x0))) 3079 return NOTIFY_DONE; 3080 3081 /* 3082 * If it is correctable error, return. 3083 */ 3084 if (mce_is_correctable(m)) 3085 return NOTIFY_OK; 3086 3087 /* 3088 * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register. 3089 */ 3090 gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET; 3091 3092 adev = find_adev(gpu_id); 3093 if (!adev) { 3094 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__, 3095 gpu_id); 3096 return NOTIFY_DONE; 3097 } 3098 3099 /* 3100 * If it is uncorrectable error, then find out UMC instance and 3101 * channel index. 3102 */ 3103 umc_inst = GET_UMC_INST(m->ipid); 3104 ch_inst = GET_CHAN_INDEX(m->ipid); 3105 3106 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d", 3107 umc_inst, ch_inst); 3108 3109 if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst)) 3110 return NOTIFY_OK; 3111 else 3112 return NOTIFY_DONE; 3113} 3114 3115static struct notifier_block amdgpu_bad_page_nb = { 3116 .notifier_call = amdgpu_bad_page_notifier, 3117 .priority = MCE_PRIO_UC, 3118}; 3119 3120static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) 3121{ 3122 /* 3123 * Add the adev to the mce_adev_list. 3124 * During mode2 reset, amdgpu device is temporarily 3125 * removed from the mgpu_info list which can cause 3126 * page retirement to fail. 3127 * Use this list instead of mgpu_info to find the amdgpu 3128 * device on which the UMC error was reported. 3129 */ 3130 mce_adev_list.devs[mce_adev_list.num_gpu++] = adev; 3131 3132 /* 3133 * Register the x86 notifier only once 3134 * with MCE subsystem. 3135 */ 3136 if (notifier_registered == false) { 3137 mce_register_decode_chain(&amdgpu_bad_page_nb); 3138 notifier_registered = true; 3139 } 3140} 3141#endif 3142 3143struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) 3144{ 3145 if (!adev) 3146 return NULL; 3147 3148 return adev->psp.ras_context.ras; 3149} 3150 3151int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con) 3152{ 3153 if (!adev) 3154 return -EINVAL; 3155 3156 adev->psp.ras_context.ras = ras_con; 3157 return 0; 3158} 3159 3160/* check if ras is supported on block, say, sdma, gfx */ 3161int amdgpu_ras_is_supported(struct amdgpu_device *adev, 3162 unsigned int block) 3163{ 3164 int ret = 0; 3165 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 3166 3167 if (block >= AMDGPU_RAS_BLOCK_COUNT) 3168 return 0; 3169 3170 ret = ras && (adev->ras_enabled & (1 << block)); 3171 3172 /* For the special asic with mem ecc enabled but sram ecc 3173 * not enabled, even if the ras block is not supported on 3174 * .ras_enabled, if the asic supports poison mode and the 3175 * ras block has ras configuration, it can be considered 3176 * that the ras block supports ras function. 3177 */ 3178 if (!ret && 3179 (block == AMDGPU_RAS_BLOCK__GFX || 3180 block == AMDGPU_RAS_BLOCK__SDMA || 3181 block == AMDGPU_RAS_BLOCK__VCN || 3182 block == AMDGPU_RAS_BLOCK__JPEG) && 3183 amdgpu_ras_is_poison_mode_supported(adev) && 3184 amdgpu_ras_get_ras_block(adev, block, 0)) 3185 ret = 1; 3186 3187 return ret; 3188} 3189 3190int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) 3191{ 3192 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 3193 3194 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) 3195 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); 3196 return 0; 3197} 3198 3199 3200/* Register each ip ras block into amdgpu ras */ 3201int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, 3202 struct amdgpu_ras_block_object *ras_block_obj) 3203{ 3204 struct amdgpu_ras_block_list *ras_node; 3205 if (!adev || !ras_block_obj) 3206 return -EINVAL; 3207 3208 ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL); 3209 if (!ras_node) 3210 return -ENOMEM; 3211 3212 INIT_LIST_HEAD(&ras_node->node); 3213 ras_node->ras_obj = ras_block_obj; 3214 list_add_tail(&ras_node->node, &adev->ras_list); 3215 3216 return 0; 3217} 3218 3219void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name) 3220{ 3221 if (!err_type_name) 3222 return; 3223 3224 switch (err_type) { 3225 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: 3226 snprintf(err_type_name, 16, "correctable"); 3227 break; 3228 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: 3229 snprintf(err_type_name, 16, "uncorrectable"); 3230 break; 3231 default: 3232 snprintf(err_type_name, 16, "unknown"); 3233 break; 3234 } 3235} 3236 3237bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, 3238 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 3239 uint32_t instance, 3240 uint32_t *memory_id) 3241{ 3242 uint32_t err_status_lo_data, err_status_lo_offset; 3243 3244 if (!reg_entry) 3245 return false; 3246 3247 err_status_lo_offset = 3248 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, 3249 reg_entry->seg_lo, reg_entry->reg_lo); 3250 err_status_lo_data = RREG32(err_status_lo_offset); 3251 3252 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) && 3253 !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG)) 3254 return false; 3255 3256 *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID); 3257 3258 return true; 3259} 3260 3261bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, 3262 const struct amdgpu_ras_err_status_reg_entry *reg_entry, 3263 uint32_t instance, 3264 unsigned long *err_cnt) 3265{ 3266 uint32_t err_status_hi_data, err_status_hi_offset; 3267 3268 if (!reg_entry) 3269 return false; 3270 3271 err_status_hi_offset = 3272 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, 3273 reg_entry->seg_hi, reg_entry->reg_hi); 3274 err_status_hi_data = RREG32(err_status_hi_offset); 3275 3276 if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) && 3277 !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG)) 3278 /* keep the check here in case we need to refer to the result later */ 3279 dev_dbg(adev->dev, "Invalid err_info field\n"); 3280 3281 /* read err count */ 3282 *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT); 3283 3284 return true; 3285} 3286 3287void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, 3288 const struct amdgpu_ras_err_status_reg_entry *reg_list, 3289 uint32_t reg_list_size, 3290 const struct amdgpu_ras_memory_id_entry *mem_list, 3291 uint32_t mem_list_size, 3292 uint32_t instance, 3293 uint32_t err_type, 3294 unsigned long *err_count) 3295{ 3296 uint32_t memory_id; 3297 unsigned long err_cnt; 3298 char err_type_name[16]; 3299 uint32_t i, j; 3300 3301 for (i = 0; i < reg_list_size; i++) { 3302 /* query memory_id from err_status_lo */ 3303 if (!amdgpu_ras_inst_get_memory_id_field(adev, ®_list[i], 3304 instance, &memory_id)) 3305 continue; 3306 3307 /* query err_cnt from err_status_hi */ 3308 if (!amdgpu_ras_inst_get_err_cnt_field(adev, ®_list[i], 3309 instance, &err_cnt) || 3310 !err_cnt) 3311 continue; 3312 3313 *err_count += err_cnt; 3314 3315 /* log the errors */ 3316 amdgpu_ras_get_error_type_name(err_type, err_type_name); 3317 if (!mem_list) { 3318 /* memory_list is not supported */ 3319 dev_info(adev->dev, 3320 "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n", 3321 err_cnt, err_type_name, 3322 reg_list[i].block_name, 3323 instance, memory_id); 3324 } else { 3325 for (j = 0; j < mem_list_size; j++) { 3326 if (memory_id == mem_list[j].memory_id) { 3327 dev_info(adev->dev, 3328 "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n", 3329 err_cnt, err_type_name, 3330 reg_list[i].block_name, 3331 instance, mem_list[j].name); 3332 break; 3333 } 3334 } 3335 } 3336 } 3337} 3338 3339void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, 3340 const struct amdgpu_ras_err_status_reg_entry *reg_list, 3341 uint32_t reg_list_size, 3342 uint32_t instance) 3343{ 3344 uint32_t err_status_lo_offset, err_status_hi_offset; 3345 uint32_t i; 3346 3347 for (i = 0; i < reg_list_size; i++) { 3348 err_status_lo_offset = 3349 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, 3350 reg_list[i].seg_lo, reg_list[i].reg_lo); 3351 err_status_hi_offset = 3352 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, 3353 reg_list[i].seg_hi, reg_list[i].reg_hi); 3354 WREG32(err_status_lo_offset, 0); 3355 WREG32(err_status_hi_offset, 0); 3356 } 3357} 3358