/openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 1096 Register Tmp = MRI->createVirtualRegister(TRI->getBoolRC()); 1099 .addReg(Tmp, getDefRegState(true))
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H A D | AMDGPULegalizerInfo.cpp | 3004 Register Tmp; 3008 Tmp = B.buildAnyExt(S64, LocalAccum[0]).getReg(0); 3011 Tmp = B.buildMergeLikeInstr(S64, LocalAccum).getReg(0); 3014 Tmp = B.buildZExt(S64, LocalAccum[0]).getReg(0); 3019 Tmp = getZero64(); 3026 {Src0[j0], Src1[j1], Tmp}); 3027 Tmp = Mad.getReg(0); 3034 auto Unmerge = B.buildUnmerge(S32, Tmp); 3190 auto Tmp = B.buildInstr(NewOpc, {DstTy}, {Src}); 3191 B.buildUMin(Dst, Tmp, [all...] |
H A D | SIInstrInfo.cpp | 629 Register Tmp = local 631 assert(MBB.getParent()->getRegInfo().isReserved(Tmp) && 641 Tmp = Tmp2; 642 RS.setRegUsed(Tmp); 653 MachineInstrBuilder UseBuilder = BuildMI(MBB, MI, DL, TII.get(TmpCopyOp), Tmp) 662 .addReg(Tmp, RegState::Kill); 2309 auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); local 2310 MovDPP.addDef(Tmp);
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/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAsmBackend.cpp | 337 SmallString<256> Tmp; local 338 raw_svector_ostream OS(Tmp);
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/openbsd-current/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86AsmBackend.cpp | 761 SmallString<256> Tmp; local 762 raw_svector_ostream OS(Tmp);
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/openbsd-current/gnu/llvm/llvm/lib/Analysis/ |
H A D | VectorUtils.cpp | 544 SmallVectorImpl<int> *Output = &TmpMasks[0], *Tmp = &TmpMasks[1]; local 549 std::swap(Output, Tmp);
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/openbsd-current/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 412 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); local 413 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), 3522 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass); local 3523 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp) 3527 Rs = Tmp; 3579 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); local 3580 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32); 3581 Rt = Tmp;
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H A D | MipsISelLowering.cpp | 4918 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); local 4921 .addDef(Tmp) 4925 .addUse(Tmp) 4931 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); local 4933 .addDef(Tmp) 4937 .addUse(Tmp) 4941 .addUse(Tmp)
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/openbsd-current/gnu/llvm/clang/lib/CodeGen/ |
H A D | CGAtomic.cpp | 1479 Address Tmp = CreateTempAlloca(); local 1480 CGF.Builder.CreateMemCpy(Tmp, Addr, 1482 Addr = Tmp;
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H A D | CGBuiltin.cpp | 678 llvm::Value *Tmp = CGF.Builder.CreateCall(Callee, {X, Y}); local 679 Carry = CGF.Builder.CreateExtractValue(Tmp, 1); 680 return CGF.Builder.CreateExtractValue(Tmp, 0); 2640 Value *Tmp = Builder.CreateSelect(IsNeg, Inverse, ArgValue); 2641 Value *Ctlz = Builder.CreateCall(F, {Tmp, Builder.getFalse()}); 2691 Value *Tmp = 2696 Value *Result = Builder.CreateSelect(IsZero, Zero, Tmp, "ffs"); 2712 Value *Tmp = Builder.CreateCall(F, ArgValue); 2713 Value *Result = Builder.CreateAnd(Tmp, llvm::ConstantInt::get(ArgType, 1)); 4950 auto Tmp [all...] |
H A D | TargetInfo.cpp | 4150 Address Tmp = CGF.CreateMemTemp(Ty); 4151 Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST); 4171 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 4177 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 4179 RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy); 4193 Address Tmp = CGF.CreateMemTemp(Ty); 4194 CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false); 4195 RegAddr = Tmp; 4220 Address Tmp [all...] |
H A D | CGCall.cpp | 1323 Address Tmp = local 1326 Tmp.getPointer(), Tmp.getAlignment().getAsAlign(), Src.getPointer(), 1329 return CGF.Builder.CreateLoad(Tmp); 1411 Address Tmp = CreateTempAllocaForCoercion(CGF, SrcTy, Dst.getAlignment()); local 1412 CGF.Builder.CreateStore(Src, Tmp); 1414 Dst.getPointer(), Dst.getAlignment().getAsAlign(), Tmp.getPointer(), 1415 Tmp.getAlignment().getAsAlign(),
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/openbsd-current/gnu/llvm/llvm/lib/Target/SPIRV/ |
H A D | SPIRVInstructionSelector.cpp | 837 Register Tmp = MRI->createVirtualRegister(&SPIRV::IDRegClass); local 843 .addDef(Tmp) 850 .addUse(Tmp)
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/openbsd-current/gnu/llvm/clang/lib/Analysis/ |
H A D | CFG.cpp | 3415 CFGBlock *Tmp = Visit(CopyExpr); local 3416 if (Tmp) 3417 LastBlock = Tmp; 3440 CFGBlock *Tmp = Visit(Init); local 3441 if (Tmp) 3442 LastBlock = Tmp;
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/openbsd-current/gnu/llvm/clang/tools/libclang/ |
H A D | CXCursor.cpp | 1254 } else if (const CXXTemporaryObjectExpr *Tmp = 1256 Type = Tmp->getTypeSourceInfo();
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/openbsd-current/gnu/llvm/clang/lib/AST/ |
H A D | DeclPrinter.cpp | 333 if (ExprWithCleanups *Tmp = dyn_cast<ExprWithCleanups>(Init)) 334 Init = Tmp->getSubExpr();
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/openbsd-current/gnu/llvm/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 4075 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift); local 4076 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp); 4081 SDValue Tmp = DAG.getSplatBuildVector(MVT::v16i8, DL, local 4083 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp); 4087 SDValue Tmp = DAG.getSplatBuildVector(MVT::v16i8, DL, local 4089 Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp); 4090 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp); 4118 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT)); local 4120 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp, 7426 unsigned Tmp = DAG.ComputeNumSignBits(PackedOp, SrcDemE, Depth + 1); local 7843 Register Tmp = MRI.createVirtualRegister(RC); local [all...] |
/openbsd-current/gnu/llvm/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 2005 Register Tmp = MRI.createVirtualRegister(&AVR::GPR8RegClass); local 2006 BuildMI(*BB, MI, dl, TII.get(AVR::ADDRdRr), Tmp) 2010 .addReg(Tmp) 2011 .addReg(Tmp);
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/openbsd-current/gnu/llvm/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 4475 SDValue Tmp = 4477 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1, dl)); 5687 SDNode *Tmp = 5690 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(Tmp, 0), 5691 N->getOperand(0), SDValue(Tmp, 1)); 5988 SDNode *Tmp = CurDAG->getMachineNode( 5995 isPPC64 ? PPC::LDtocL : PPC::LWZtocL, dl, VT, GA, SDValue(Tmp, 0)); 6004 SDValue(Tmp, 0), GA)); 6054 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 6055 SDValue TmpVal = SDValue(Tmp, [all...] |
/openbsd-current/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonLoopIdiomRecognition.cpp | 1561 unsigned Tmp = (QI->getZExtValue() | 1) & M; local 1562 unsigned QV = getInverseMxN(Tmp) & M;
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/openbsd-current/gnu/llvm/clang/include/clang/AST/ |
H A D | DeclObjC.h | 1610 filtered_category_iterator Tmp = *this; local 1612 return Tmp;
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/openbsd-current/gnu/llvm/llvm/lib/ObjectYAML/ |
H A D | ELFYAML.cpp | 1529 APInt Tmp; local 1530 return !Val.getAsInteger(0, Tmp);
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/openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 2538 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0)); 2540 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp); 3511 char Tmp[] = {'{', RegType, RegIndex, '}', 0}; local 3512 return getRegForInlineAsmConstraint(TRI, Tmp, VT);
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/openbsd-current/gnu/llvm/llvm/lib/Target/VE/ |
H A D | VEISelLowering.cpp | 2322 Register Tmp = MRI.createVirtualRegister(&VE::I64RegClass); local 2348 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), Tmp); 2369 .addReg(Tmp, getKillRegState(true))
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/openbsd-current/gnu/llvm/llvm/lib/ExecutionEngine/Orc/ |
H A D | Core.cpp | 2433 SymbolLookupSet Tmp; 2434 std::swap(IPLS->DefGeneratorNonCandidates, Tmp); 2435 IPLS->DefGeneratorCandidates.append(std::move(Tmp));
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