/netbsd-current/sys/arch/arm/sunxi/ |
H A D | sun8i_h3_codec.c | 128 #define WR4(sc, reg, val) \ macro 157 WR4(csc, H3_PR_CFG, val); 161 WR4(csc, H3_PR_CFG, val); 166 WR4(csc, H3_PR_CFG, val); 182 WR4(csc, H3_PR_CFG, val); 187 WR4(csc, H3_PR_CFG, val); 192 WR4(csc, H3_PR_CFG, val); 196 WR4(csc, H3_PR_CFG, val); 200 WR4(csc, H3_PR_CFG, val);
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H A D | sun8i_v3s_codec.c | 115 #define WR4(sc, reg, val) \ macro 144 WR4(csc, V3S_PR_CFG, val); 148 WR4(csc, V3S_PR_CFG, val); 153 WR4(csc, V3S_PR_CFG, val); 169 WR4(csc, V3S_PR_CFG, val); 174 WR4(csc, V3S_PR_CFG, val); 179 WR4(csc, V3S_PR_CFG, val); 183 WR4(csc, V3S_PR_CFG, val); 187 WR4(csc, V3S_PR_CFG, val);
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H A D | sunxi_emac.c | 202 #define WR4(sc, reg, val) \ macro 211 WR4(sc, EMAC_MII_CMD, 239 WR4(sc, EMAC_MII_DATA, val); 240 WR4(sc, EMAC_MII_CMD, 280 WR4(sc, EMAC_BASIC_CTL_0, val); 286 WR4(sc, EMAC_RX_CTL_0, val); 294 WR4(sc, EMAC_TX_FLOW_CTL, val); 488 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 574 WR4(sc, EMAC_ADDR_HIGH(0), machi); 575 WR4(s [all...] |
H A D | sun4i_a10_codec.c | 110 #define WR4(sc, reg, val) \ macro 113 WR4((sc), (reg), RD4((sc), (reg)) | (mask)) 115 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask)) 165 WR4(sc, mix->reg, val);
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H A D | sun50i_a64_acodec.c | 155 #define WR4(sc, reg, val) \ macro 168 WR4(sc, A64_PR_CFG, val); 172 WR4(sc, A64_PR_CFG, val); 177 WR4(sc, A64_PR_CFG, val); 193 WR4(sc, A64_PR_CFG, val); 198 WR4(sc, A64_PR_CFG, val); 203 WR4(sc, A64_PR_CFG, val); 207 WR4(sc, A64_PR_CFG, val); 211 WR4(sc, A64_PR_CFG, val);
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H A D | sun6i_a31_codec.c | 153 #define WR4(sc, reg, val) \ macro 156 WR4((sc), (reg), RD4((sc), (reg)) | (mask)) 158 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask)) 226 WR4(sc, mix->reg, val);
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H A D | sunxi_gmacclk.c | 86 #define WR4(sc, reg, val) \ macro 192 WR4(sc, 0, val);
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H A D | sun8i_a23_apbclk.c | 80 #define WR4(sc, reg, val) \ macro
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/netbsd-current/sys/arch/evbppc/wii/dev/ |
H A D | hwgpio.c | 84 #define WR4(reg, val) out32((reg), (val)) macro 105 WR4(HW_GPIOB_OUT, out); 122 WR4(HW_GPIOB_DIR, dir);
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/netbsd-current/sys/arch/arm/xilinx/ |
H A D | zynq_xadc.c | 149 #define WR4(sc, reg, val) \ macro 172 WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_WRITE, reg, data)); 207 WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_READ, reg, 0)); 208 WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_NOP, 0, 0)); 236 WR4(sc, XADCIF_CFG, val); 237 WR4(sc, XADCIF_MCTL, 0);
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H A D | zynq_gpio.c | 80 #define WR4(sc, reg, val) \ macro 108 WR4(sc, OEN_REG(pin), oen); 109 WR4(sc, DIRM_REG(pin), dirm); 224 WR4(sc, MASK_DATA_REG(pin), mask_data);
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/netbsd-current/sys/arch/arm/rockchip/ |
H A D | rk_gpio.c | 104 #define WR4(sc, reg, val) \ macro 224 WR4(sc, GPIO_SWPORTA_DR_REG, data); 242 WR4(sc, GPIO_SWPORTA_DDR_REG, ddr); 276 WR4(sc, GPIOV2_SWPORT_DR_REG(pin), write_mask | data); 289 WR4(sc, GPIOV2_SWPORT_DDR_REG(pin), GPIOV2_WRITE_MASK(pin) | ddr);
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H A D | rk3399_iomux.c | 202 #define WR4(syscon, reg, val) \ macro 250 WR4(syscon, reg, bias_val | bias_mask); 342 WR4(syscon, reg, write_val | write_mask); 376 WR4(syscon, reg, (mask << 16) | __SHIFTIN(mux, mask)); 475 WR4(syscon, GRF_GPIO4B_IOMUX, val); 478 WR4(syscon, GRF_SOC_CON7, val);
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H A D | rk3328_iomux.c | 135 #define WR4(sc, reg, val) \ macro 166 WR4(sc, GRF_GPIO_P_REG(bank, idx), 174 WR4(sc, GRF_GPIO_E_REG(bank, idx), 187 WR4(sc, reg, (mask << 16) | __SHIFTIN(mux, mask));
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H A D | rk3288_iomux.c | 85 #define WR4(reg, off, val) \ macro 190 WR4(reg, reg->pull_reg, val); 224 WR4(reg, reg->drv_reg, val); 243 WR4(reg, reg->mux_reg, val);
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/netbsd-current/sys/arch/luna68k/stand/boot/ |
H A D | sio.c | 226 sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY); 242 sioreg(REG(1, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY);
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H A D | sioreg.h | 96 #define WR4 0x04 macro
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/netbsd-current/sys/arch/arm/ti/ |
H A D | ti_lcdc.h | 124 #define WR4(sc, reg, val) \ macro
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H A D | ti_usb.c | 125 #define WR4(sc, reg, val) \ macro 141 WR4(sc, UHH_SYSCONFIG, val); 159 WR4(sc, UHH_HOSTCONFIG, val);
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H A D | ti_mux_clock.c | 81 #define WR4(sc, reg, val) \ macro 212 WR4(sc, 0, val);
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H A D | ti_div_clock.c | 80 #define WR4(sc, val) \ macro
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/netbsd-current/sys/arch/luna68k/dev/ |
H A D | sioreg.h | 77 #define WR4 0x04 macro
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H A D | siotty.c | 193 setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]); 449 sc->sc_wr[WR4] = wr4; 452 setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]); 722 setsioreg(sio, WR4, ch0_regs[WR4]);
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/netbsd-current/sys/arch/riscv/sifive/ |
H A D | fu540_prci.c | 88 #define WR4(sc, reg, val) \ macro 165 WR4(sc, DDRPLLCFG1, val | PLL1_CKE); 169 WR4(sc, GEMGXLPLLCFG1, val | PLL1_CKE);
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H A D | fu540_ccache.c | 100 #define WR4(sc, reg, val) \ macro 123 WR4(sc, CCACHE_FLUSH32, fpa >> 4);
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