Searched refs:WR4 (Results 26 - 50 of 56) sorted by relevance

123

/netbsd-current/sys/arch/arm/sunxi/
H A Dsun8i_h3_codec.c128 #define WR4(sc, reg, val) \ macro
157 WR4(csc, H3_PR_CFG, val);
161 WR4(csc, H3_PR_CFG, val);
166 WR4(csc, H3_PR_CFG, val);
182 WR4(csc, H3_PR_CFG, val);
187 WR4(csc, H3_PR_CFG, val);
192 WR4(csc, H3_PR_CFG, val);
196 WR4(csc, H3_PR_CFG, val);
200 WR4(csc, H3_PR_CFG, val);
H A Dsun8i_v3s_codec.c115 #define WR4(sc, reg, val) \ macro
144 WR4(csc, V3S_PR_CFG, val);
148 WR4(csc, V3S_PR_CFG, val);
153 WR4(csc, V3S_PR_CFG, val);
169 WR4(csc, V3S_PR_CFG, val);
174 WR4(csc, V3S_PR_CFG, val);
179 WR4(csc, V3S_PR_CFG, val);
183 WR4(csc, V3S_PR_CFG, val);
187 WR4(csc, V3S_PR_CFG, val);
H A Dsunxi_emac.c202 #define WR4(sc, reg, val) \ macro
211 WR4(sc, EMAC_MII_CMD,
239 WR4(sc, EMAC_MII_DATA, val);
240 WR4(sc, EMAC_MII_CMD,
280 WR4(sc, EMAC_BASIC_CTL_0, val);
286 WR4(sc, EMAC_RX_CTL_0, val);
294 WR4(sc, EMAC_TX_FLOW_CTL, val);
488 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
574 WR4(sc, EMAC_ADDR_HIGH(0), machi);
575 WR4(s
[all...]
H A Dsun4i_a10_codec.c110 #define WR4(sc, reg, val) \ macro
113 WR4((sc), (reg), RD4((sc), (reg)) | (mask))
115 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
165 WR4(sc, mix->reg, val);
H A Dsun50i_a64_acodec.c155 #define WR4(sc, reg, val) \ macro
168 WR4(sc, A64_PR_CFG, val);
172 WR4(sc, A64_PR_CFG, val);
177 WR4(sc, A64_PR_CFG, val);
193 WR4(sc, A64_PR_CFG, val);
198 WR4(sc, A64_PR_CFG, val);
203 WR4(sc, A64_PR_CFG, val);
207 WR4(sc, A64_PR_CFG, val);
211 WR4(sc, A64_PR_CFG, val);
H A Dsun6i_a31_codec.c153 #define WR4(sc, reg, val) \ macro
156 WR4((sc), (reg), RD4((sc), (reg)) | (mask))
158 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
226 WR4(sc, mix->reg, val);
H A Dsunxi_gmacclk.c86 #define WR4(sc, reg, val) \ macro
192 WR4(sc, 0, val);
H A Dsun8i_a23_apbclk.c80 #define WR4(sc, reg, val) \ macro
/netbsd-current/sys/arch/evbppc/wii/dev/
H A Dhwgpio.c84 #define WR4(reg, val) out32((reg), (val)) macro
105 WR4(HW_GPIOB_OUT, out);
122 WR4(HW_GPIOB_DIR, dir);
/netbsd-current/sys/arch/arm/xilinx/
H A Dzynq_xadc.c149 #define WR4(sc, reg, val) \ macro
172 WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_WRITE, reg, data));
207 WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_READ, reg, 0));
208 WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_NOP, 0, 0));
236 WR4(sc, XADCIF_CFG, val);
237 WR4(sc, XADCIF_MCTL, 0);
H A Dzynq_gpio.c80 #define WR4(sc, reg, val) \ macro
108 WR4(sc, OEN_REG(pin), oen);
109 WR4(sc, DIRM_REG(pin), dirm);
224 WR4(sc, MASK_DATA_REG(pin), mask_data);
/netbsd-current/sys/arch/arm/rockchip/
H A Drk_gpio.c104 #define WR4(sc, reg, val) \ macro
224 WR4(sc, GPIO_SWPORTA_DR_REG, data);
242 WR4(sc, GPIO_SWPORTA_DDR_REG, ddr);
276 WR4(sc, GPIOV2_SWPORT_DR_REG(pin), write_mask | data);
289 WR4(sc, GPIOV2_SWPORT_DDR_REG(pin), GPIOV2_WRITE_MASK(pin) | ddr);
H A Drk3399_iomux.c202 #define WR4(syscon, reg, val) \ macro
250 WR4(syscon, reg, bias_val | bias_mask);
342 WR4(syscon, reg, write_val | write_mask);
376 WR4(syscon, reg, (mask << 16) | __SHIFTIN(mux, mask));
475 WR4(syscon, GRF_GPIO4B_IOMUX, val);
478 WR4(syscon, GRF_SOC_CON7, val);
H A Drk3328_iomux.c135 #define WR4(sc, reg, val) \ macro
166 WR4(sc, GRF_GPIO_P_REG(bank, idx),
174 WR4(sc, GRF_GPIO_E_REG(bank, idx),
187 WR4(sc, reg, (mask << 16) | __SHIFTIN(mux, mask));
H A Drk3288_iomux.c85 #define WR4(reg, off, val) \ macro
190 WR4(reg, reg->pull_reg, val);
224 WR4(reg, reg->drv_reg, val);
243 WR4(reg, reg->mux_reg, val);
/netbsd-current/sys/arch/luna68k/stand/boot/
H A Dsio.c226 sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY);
242 sioreg(REG(1, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY);
H A Dsioreg.h96 #define WR4 0x04 macro
/netbsd-current/sys/arch/arm/ti/
H A Dti_lcdc.h124 #define WR4(sc, reg, val) \ macro
H A Dti_usb.c125 #define WR4(sc, reg, val) \ macro
141 WR4(sc, UHH_SYSCONFIG, val);
159 WR4(sc, UHH_HOSTCONFIG, val);
H A Dti_mux_clock.c81 #define WR4(sc, reg, val) \ macro
212 WR4(sc, 0, val);
H A Dti_div_clock.c80 #define WR4(sc, val) \ macro
/netbsd-current/sys/arch/luna68k/dev/
H A Dsioreg.h77 #define WR4 0x04 macro
H A Dsiotty.c193 setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]);
449 sc->sc_wr[WR4] = wr4;
452 setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]);
722 setsioreg(sio, WR4, ch0_regs[WR4]);
/netbsd-current/sys/arch/riscv/sifive/
H A Dfu540_prci.c88 #define WR4(sc, reg, val) \ macro
165 WR4(sc, DDRPLLCFG1, val | PLL1_CKE);
169 WR4(sc, GEMGXLPLLCFG1, val | PLL1_CKE);
H A Dfu540_ccache.c100 #define WR4(sc, reg, val) \ macro
123 WR4(sc, CCACHE_FLUSH32, fpa >> 4);

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