Lines Matching refs:WR4
202 #define WR4(sc, reg, val) \
211 WR4(sc, EMAC_MII_CMD,
239 WR4(sc, EMAC_MII_DATA, val);
240 WR4(sc, EMAC_MII_CMD,
280 WR4(sc, EMAC_BASIC_CTL_0, val);
286 WR4(sc, EMAC_RX_CTL_0, val);
294 WR4(sc, EMAC_TX_FLOW_CTL, val);
488 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
574 WR4(sc, EMAC_ADDR_HIGH(0), machi);
575 WR4(sc, EMAC_ADDR_LOW(0), maclo);
578 WR4(sc, EMAC_RX_HASH_0, hash[1]);
579 WR4(sc, EMAC_RX_HASH_1, hash[0]);
582 WR4(sc, EMAC_RX_FRM_FLT, val);
589 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
596 WR4(sc, EMAC_INT_EN, 0);
646 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
681 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
682 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
690 WR4(sc, EMAC_BASIC_CTL_1, val);
697 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME);
701 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD);
705 WR4(sc, EMAC_TX_CTL_0, val | TX_EN);
709 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC);
748 WR4(sc, EMAC_TX_CTL_1, val);
752 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN);
756 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN);
763 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN);
767 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN);
901 WR4(sc, EMAC_INT_STA, val);