| /netbsd-current/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| H A D | c_dsp32shiftim_af.s | 24 R5 = R5 << 24; define
49 R3 = R5 >>> 24;
51 R5 = R7 >>> 20; define
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| H A D | c_dsp32shiftim_af_s.s | 24 R5 = R5 << 24 (S); define
49 R3 = R5 >>> 24;
51 R5 = R7 >>> 20; define
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| H A D | c_dsp32shiftim_ahh.s | 25 R5 = R5 << 15 (V); define
50 R4 = R5 >>> 4 (V);
51 R5 = R6 >>> 9 (V); define
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| H A D | c_dsp32shiftim_ahh_s.s | 25 R5 = R5 << 15 (V , S); define
50 R4 = R5 >>> 4 (V, S);
51 R5 = R6 >>> 9 (V, S); define
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| H A D | c_dsp32shiftim_lf.s | 24 R5 = R5 << 24; define
49 R3 = R5 >> 24;
51 R5 = R7 >> 20; define
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| H A D | c_dsp32shiftim_lhh.s | 25 R5 = R5 << 15 (V); define
50 R4 = R5 >> 2 (V);
51 R5 = R6 >> 9 (V); define
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| H A D | c_dsp32shiftim_rot.s | 25 R5 = ROT R5 BY 31; define
50 R3 = ROT R5 BY -24;
52 R5 = ROT R7 BY -22; define
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| H A D | c_regmv_dr_dr.s | 22 R5 = R0; define
47 R5 = R1; define
72 R5 = R2; define
97 R5 = R3; define
122 R5 = R4; define
142 R0 = R5;
143 R1 = R5;
144 R2 = R5;
145 R3 = R5;
146 R4 = R5;
147 R5 = R5; define
172 R5 = R6; define
197 R5 = R7; define
[all...] |
| H A D | s1.s | 12 R5 = 5; define
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| H A D | se_loop_nest_ppm_2.S | 351 l1s:R5 += 1;
356 l2s:R5 += 1;
362 l3s:R5 += 1;
369 l4s:R5 += 1;
377 l5s:R5 += 1;
381 R5 += 3;
386 l6s:R5 += 1;
390 R5 += 3;
402 m1s:R5 += 1;
407 m2s:R5
[all...] |
| H A D | se_loop_ppm.S | 348 l1s:R5 += 1;
352 l2s:R5 += 1;
357 l3s:R5 += 1;
363 l4s:R5 += 1;
370 l5s:R5 += 1;
374 R5 += 3;
378 l6s:R5 += 1;
382 R5 += 3;
392 m1s:R5 += 1;
396 m2s:R5
[all...] |
| H A D | 10272_small.s | 18 R5=W[P5+0x6] (X);
33 R5=W[P5+0x6] (X);
44 R5=W[P5+0x6] (X);
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| H A D | a8.s | 12 R5.L = 5; R5.H = 0;
37 R5 = R0.L; define
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| H A D | c_dsp32alu_awx.s | 28 R5.L = A0.x;
35 R5 = ( A0 += A1 ); define
56 R5 = A1.w; define
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| /netbsd-current/external/gpl3/gdb.old/dist/sim/testsuite/sim/bfin/ |
| H A D | 10272_small.s | 18 R5=W[P5+0x6] (X);
33 R5=W[P5+0x6] (X);
44 R5=W[P5+0x6] (X);
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| H A D | a8.s | 12 R5.L = 5; R5.H = 0;
37 R5 = R0.L; define
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| H A D | c_dsp32alu_awx.s | 28 R5.L = A0.x;
35 R5 = ( A0 += A1 ); define
56 R5 = A1.w; define
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| H A D | c_dsp32mac_dr_a0.s | 35 A1 = R4.L * R5.L, R4.L = ( A0 += R4.H * R5.H );
36 R5 = A0.w; define
60 A1 = R4.H * R5.H, R4.L = ( A0 += R4.H * R5.H );
61 R5 = A0.w; define
85 A1 -= R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H );
86 R5 = A0.w; define
110 A1 = R4.H * R5
111 R5 = A0.w; define
[all...] |
| H A D | c_dsp32shift_pack.s | 22 R5 = PACK( R4.L , R0.L ); define
23 R6 = PACK( R5.L , R0.H );
46 R5 = PACK( R3.H , R1.H ); define
48 R7 = PACK( R5.L , R1.H );
70 R5 = PACK( R2.H , R2.L ); define
73 R0 = PACK( R5.L , R2.H );
94 R5 = PACK( R1.L , R3.H ); define
98 R1 = PACK( R5.L , R3.H );
123 R5 = PACK( R5 define
150 R5 = PACK( R7.H , R5.H ); define
174 R5 = PACK( R6.H , R6.L ); define
198 R5 = PACK( R5.L , R7.H ); define
223 R5 = PACK( R5.L , R0.H ); define
248 R5 = PACK( R5.L , R1.H ); define
274 R5 = PACK( R5.L , R2.H ); define
299 R5 = PACK( R5.L , R3.H ); define
324 R5 = PACK( R5.L , R4.H ); define
349 R5 = PACK( R5.L , R5.H ); define
375 R5 = PACK( R5.L , R6.H ); define
400 R5 = PACK( R5.L , R7.H ); define
[all...] |
| H A D | c_dsp32shift_vmaxvmax.s | 23 R5 = VIT_MAX( R5 , R4 ) (ASL); define
24 R6 = VIT_MAX( R6 , R5 ) (ASL);
47 R4 = VIT_MAX( R4 , R5 ) (ASL);
48 R5 = VIT_MAX( R5 , R7 ) (ASL); define
73 R5 = VIT_MAX( R5 , R4 ) (ASR); define
74 R6 = VIT_MAX( R6 , R5 ) (ASR);
95 R1 = VIT_MAX( R5 , R
99 R5 = VIT_MAX( R1 , R5 ) (ASR); define
[all...] |
| H A D | c_ldimmhalf_dreg.s | 18 R5 = 0x5678 (X); define
35 R5 = -5555 (X); define
52 R5 = -32767 (X); define
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| H A D | c_pushpopmultiple_dreg.s | 18 R5 = 0x06; define
27 R5 = 0; define
44 R5 = 0x16; define
52 R5 = 0; define
68 R5 = 0x26; define
75 R5 = 0; define
90 R5 = 0x36; define
96 R5 = 0; define
110 R5 = 0x46 (X); define
115 R5 define
128 R5 = 0x56 (X); define
132 R5 = 0; define
[all...] |
| H A D | lmu_excpt_default.S | 54 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
73 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
94 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
113 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
144 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
163 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
183 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
202 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
223 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
242 R4 = 0;R5
[all...] |
| H A D | random_0007.S | 16 imm32 R5, 0xffb58000;
18 (R4, R5) = SEARCH R6 (GE);
33 imm32 R5, 0x386ab3f7;
35 (R5, R1) = SEARCH R7 (GT);
50 imm32 R5, 0x386ab3f7;
52 (R5, R1) = SEARCH R7 (GT);
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| H A D | usp.S | 10 imm32 R5, 0x44455566
32 SP = R5;
44 CC = R1 == R5;
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