1//Original:/testcases/core/c_dsp32shiftim_ahh_s/c_dsp32shiftim_ahh_s.dsp 2# mach: bfin 3 4.include "testutils.inc" 5 start 6 7 8// Spec Reference: dsp32shiftimm ashift: ashift / ashift saturated 9 10 11 12imm32 r0, 0x01230abc; 13imm32 r1, 0x12345678; 14imm32 r2, 0x23456789; 15imm32 r3, 0x3456789a; 16imm32 r4, 0x456789ab; 17imm32 r5, 0x56789abc; 18imm32 r6, 0x6789abcd; 19imm32 r7, 0x789abcde; 20R0 = R0 << 0 (V , S); 21R1 = R1 << 3 (V , S); 22R2 = R2 << 5 (V , S); 23R3 = R3 << 8 (V , S); 24R4 = R4 << 9 (V , S); 25R5 = R5 << 15 (V , S); 26R6 = R6 << 7 (V , S); 27R7 = R7 << 13 (V , S); 28CHECKREG r0, 0x01230ABC; 29CHECKREG r1, 0x7FFF7FFF; 30CHECKREG r2, 0x7FFF7FFF; 31CHECKREG r3, 0x7FFF7FFF; 32CHECKREG r4, 0x7FFF8000; 33CHECKREG r5, 0x7FFF8000; 34CHECKREG r6, 0x7FFF8000; 35CHECKREG r7, 0x7FFF8000; 36 37imm32 r0, 0x01230000; 38imm32 r1, 0x12345678; 39imm32 r2, 0x23456789; 40imm32 r3, 0x3456789a; 41imm32 r4, 0x456789ab; 42imm32 r5, 0x56789abc; 43imm32 r6, 0x6789abcd; 44imm32 r7, 0x789abcde; 45R7 = R0 >>> 1 (V, S); 46R0 = R1 >>> 8 (V, S); 47R1 = R2 >>> 14 (V, S); 48R2 = R3 >>> 15 (V, S); 49R3 = R4 >>> 11 (V, S); 50R4 = R5 >>> 4 (V, S); 51R5 = R6 >>> 9 (V, S); 52R6 = R7 >>> 6 (V, S); 53CHECKREG r0, 0x00120056; 54CHECKREG r1, 0x00000001; 55CHECKREG r2, 0x00000000; 56CHECKREG r3, 0x0008FFF1; 57CHECKREG r4, 0x0567F9AB; 58CHECKREG r5, 0x0033FFD5; 59CHECKREG r6, 0x00020000; 60CHECKREG r7, 0x00910000; 61 62 63 64 65pass 66