1//Original:/testcases/core/c_dsp32mac_dr_a0/c_dsp32mac_dr_a0.dsp 2// Spec Reference: dsp32mac dr_a0 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10 11imm32 r0, 0xab235675; 12imm32 r1, 0xcaba5127; 13imm32 r2, 0x13a46705; 14imm32 r3, 0x000a0007; 15imm32 r4, 0x90abad09; 16imm32 r5, 0x10aceadb; 17imm32 r6, 0x000c00ad; 18imm32 r7, 0x1246700a; 19 20A1 = A0 = 0; 21 22// The result accumulated in A1 , and stored to a reg half 23imm32 r0, 0xb3545abd; 24imm32 r1, 0xabbcfec7; 25imm32 r2, 0xa1b45679; 26imm32 r3, 0x000b0007; 27imm32 r4, 0xefbcb569; 28imm32 r5, 0x12350b0b; 29imm32 r6, 0x000c00bd; 30imm32 r7, 0x678e000b; 31A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); 32R1 = A0.w; 33A1 -= R2.L * R3.L, R2.L = ( A0 = R2.H * R3.L ); 34R3 = A0.w; 35A1 = R4.L * R5.L, R4.L = ( A0 += R4.H * R5.H ); 36R5 = A0.w; 37A1 = R6.L * R7.L, R6.L = ( A0 = R6.L * R7.H ); 38R7 = A0.w; 39CHECKREG r0, 0xB354FF22; 40CHECKREG r1, 0xFF221DD6; 41CHECKREG r2, 0xA1B4FFFB; 42CHECKREG r3, 0xFFFAD7D8; 43CHECKREG r4, 0xEFBCFDAB; 44CHECKREG r5, 0xFDAA8BB0; 45CHECKREG r6, 0x000C0099; 46CHECKREG r7, 0x0098E7AC; 47 48imm32 r0, 0xc3545abd; 49imm32 r1, 0xacbcfec7; 50imm32 r2, 0xa1c45679; 51imm32 r3, 0x000c0007; 52imm32 r4, 0xefbcc569; 53imm32 r5, 0x12350c0b; 54imm32 r6, 0x000c00cd; 55imm32 r7, 0x678e000c; 56A1 = R1.L * R0.H, R0.L = ( A0 = R1.L * R0.L ); 57R1 = A0.w; 58A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ); 59R3 = A0.w; 60A1 = R4.H * R5.H, R4.L = ( A0 += R4.H * R5.H ); 61R5 = A0.w; 62A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ); 63R7 = A0.w; 64CHECKREG r0, 0xC354FF22; 65CHECKREG r1, 0xFF221DD6; 66CHECKREG r2, 0xA1C4FF27; 67CHECKREG r3, 0xFF27451E; 68CHECKREG r4, 0xEFBCFCD7; 69CHECKREG r5, 0xFCD6F8F6; 70CHECKREG r6, 0x000CFD7D; 71CHECKREG r7, 0xFD7CD262; 72 73imm32 r0, 0xd3545abd; 74imm32 r1, 0xadbcfec7; 75imm32 r2, 0xa1d45679; 76imm32 r3, 0x000d0007; 77imm32 r4, 0xefbcd569; 78imm32 r5, 0x12350d0b; 79imm32 r6, 0x000c00dd; 80imm32 r7, 0x678e000d; 81A1 += R1.H * R0.L, R0.L = ( A0 -= R1.L * R0.L ); 82R1 = A0.w; 83A1 = R2.H * R3.H, R2.L = ( A0 -= R2.H * R3.L ); 84R3 = A0.w; 85A1 -= R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ); 86R5 = A0.w; 87A1 += R6.H * R7.L, R6.L = ( A0 = R6.L * R7.H ); 88R7 = A0.w; 89CHECKREG r0, 0xD354FE5B; 90CHECKREG r1, 0xFE5AB48C; 91CHECKREG r2, 0xA1D4FE60; 92CHECKREG r3, 0xFE5FDAF4; 93CHECKREG r4, 0xEFBC00B0; 94CHECKREG r5, 0x00B0271C; 95CHECKREG r6, 0x000C00B3; 96CHECKREG r7, 0x00B2CB2C; 97 98imm32 r0, 0xe3545abd; 99imm32 r1, 0xaebcfec7; 100imm32 r2, 0xa1e45679; 101imm32 r3, 0x000e0007; 102imm32 r4, 0xefbce569; 103imm32 r5, 0x12350e0b; 104imm32 r6, 0x000c00ed; 105imm32 r7, 0x678e000e; 106A1 = R1.H * R0.H, R0.L = ( A0 = R1.L * R0.L ); 107R1 = A0.w; 108A1 += R2.H * R3.H, R2.L = ( A0 += R2.H * R3.L ); 109R3 = A0.w; 110A1 = R4.H * R5.H, R4.L = ( A0 = R4.H * R5.H ); 111R5 = A0.w; 112A1 = R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ); 113R7 = A0.w; 114CHECKREG r0, 0xE354FF22; 115CHECKREG r1, 0xFF221DD6; 116CHECKREG r2, 0xA1E4FF1D; 117CHECKREG r3, 0xFF1CF84E; 118CHECKREG r4, 0xEFBCFDB0; 119CHECKREG r5, 0xFDAFB3D8; 120CHECKREG r6, 0x000CFCF0; 121CHECKREG r7, 0xFCEFF6EC; 122 123 124pass 125