Searched refs:x10 (Results 301 - 325 of 3017) sorted by relevance

<<11121314151617181920>>

/netbsd-6-1-5-RELEASE/sys/dev/ic/
H A Dmb86960reg.h109 #define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */
119 #define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */
162 #define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */
170 #define FE_D6_BBW 0x10 /* Buffer SRAM bus width */
186 #define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */
201 #define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */
281 #define FE_B15_RMTPRT 0x10 /* ??? */
348 #define FE_RXSTAT_RMT0900 0x10
357 #define FE_MBH0 0x10 /* Master interrupt register */
360 #define FE_MBH0_INTR_ENABLE 0x10 /* Enabl
[all...]
H A Dct65550reg.h85 #define CT_BLT_CONTROL 0x10
140 #define FB_SWAP_16 0x10
151 #define BLITTER_16BIT 0x10
158 #define EXTENDED_TEXT 0x10
177 #define DDC_HV_POWERDOWN 0x10
198 #define ENABLE_CURSOR_1 0x10
288 #define USE_MEM_CLOCK 0x10
299 #define HOST_STANDBY 0x10
314 #define FP_TEXT_VIDEO_INVERT 0x10
323 #define MEM_DRIVE_HIGHER 0x10
[all...]
H A Dam7930reg.h13 #define AM7930_IR_BBUFF 0x10 /* Bb or Bc byte avail/empty */
50 #define AM7930_INIT_CDS_DIV4 0x10
106 #define AM7930_MMR1_X 0x10
115 #define AM7930_MMR2_RNG 0x10
124 #define AM7930_MMR3_GA6 0x10
159 #define AM7930_PPCR1_IOM2SL 0x10
H A Dibm561reg.h52 #define CR1_OVL_16BPP 0x10
63 #define CR2_ENABLE_PLL 0x10
77 #define CR3_ENABLE_MISR 0x10 /* diagnostic mode */
101 #define CURS_OVERLAP_OR 0x10
119 #define XHAIR_CLIP_WINDOW 0x10 /* use window registers */
208 #define AUXOL_UNDERLAY_ENABLE 0x10
H A Dmc146818reg.h96 #define MC_REGB_UIE 0x10 /* Update End interrupt enable */
104 #define MC_REGC_UF 0x10 /* Update End interrupt flag */
145 #define MC_BASE_1_MHz 0x10 /* 1 MHz crystal */
/netbsd-6-1-5-RELEASE/sys/arch/mmeye/dev/
H A Dmmeyepcmciareg.h69 #define MMEYEPCMCIA_IF_STATUS_MEM_WP 0x10
84 #define MMEYEPCMCIA_PWRCTL_PWR_ENABLE 0x10
100 #define MMEYEPCMCIA_CSC_GPI 0x10
111 #define MMEYEPCMCIA_ADDRWIN_ENABLE_MEM4 0x10
120 #define MMEYEPCMCIA_CARD_DETECT_RESUME_ENABLE 0x10
134 #define MMEYEPCMCIA_INTR_ENABLE 0x10
160 #define MMEYEPCMCIA_CSC_INTR_IRQ_RESERVED1 0x10
193 #define MMEYEPCMCIA_IOCTL_IO1_DATASIZE_MASK 0x10
194 #define MMEYEPCMCIA_IOCTL_IO1_DATASIZE_16BIT 0x10
255 #define MMEYEPCMCIA_SYSMEM_ADDR0_START_LSB 0x10
[all...]
/netbsd-6-1-5-RELEASE/usr.sbin/moused/
H A Dmouse.h197 #define MOUSE_MSS_BUTTON3DOWN 0x10 /* right */
204 #define MOUSE_ALPS_TAP 0x10 /* `tapping' action, the 4th byte */
208 #define MOUSE_THINK_BUTTON4DOWN 0x10 /* lower-right button, the 4th byte */
212 #define MOUSE_INTELLI_BUTTON2DOWN 0x10 /* middle button in the 4th byte */
232 #define MOUSE_MM_XPOSITIVE 0x10
248 #define MOUSE_PS2_XNEG 0x10
257 #define MOUSE_PS2PLUS_BUTTON4DOWN 0x10 /* 4th button on MouseMan+ */
273 #define MOUSE_EXPLORER_BUTTON4DOWN 0x10
284 #define MOUSE_VERSA_BUTTON3DOWN 0x10 /* right */
289 #define MOUSE_PS2VERSA_IN_USE 0x10
[all...]
/netbsd-6-1-5-RELEASE/sys/dev/hpc/
H A Dbifont.c87 /* code 1c */ 0x07,0x0f,0x1f,0x18,0x18,0x10,0x1e,0x17,
90 /* code 1f */ 0x04,0x28,0xd8,0x28,0xd0,0x10,0xe0,0x00,
98 /* code 27 */ 0x0c,0x08,0x10,0x00,0x00,0x00,0x00,0x00,
99 /* code 28 */ 0x04,0x08,0x10,0x10,0x10,0x08,0x04,0x00,
100 /* code 29 */ 0x10,0x08,0x04,0x04,0x04,0x08,0x10,0x00,
103 /* code 2c */ 0x00,0x00,0x00,0x00,0x00,0x18,0x10,0x20,
106 /* code 2f */ 0x04,0x04,0x08,0x08,0x10,
[all...]
/netbsd-6-1-5-RELEASE/sys/arch/sparc64/dev/
H A Dpsmreg.h63 #define PSM_ISR_LIDC 0x10 /* Transition to clamshell open */
74 #define PSM_STAT_ERR 0x10 /* Hardware error occured */
107 #define PSM_MCR_SD 0x10 /* Shutdown permission granted */
149 #define PSM_BCB_CHG 0x10 /* Battery pack charging */
158 #define PSM_MISC_BLITE 0x10 /* Backlight intensity register */
196 #define PSM_IMR_MLIDC 0x10 /* Lid close interrupt */
/netbsd-6-1-5-RELEASE/sys/arch/newsmips/apbus/
H A Dspifireg.h108 #define INTR_DERR 0x10
118 #define PRS_CD 0x10
131 #define FIFOC_SSTKACT 0x10 /* Synchronous stack active (?) */
140 #define CONFIG_PCHKEN 0x10 /* Parity checking enable */
160 #define PRC_CLRACK 0x10
178 #define ICOND_SVPTEXP 0x10
/netbsd-6-1-5-RELEASE/sys/arch/sh3/include/
H A Dscifreg.h71 #define SCIF_SSR 0x10 /* serial status */
111 #define SCSMR2_O 0x10 /* parity mode Odd */
120 #define SCSMR2_ICK1 0x10
128 #define SCSCR2_RE 0x10 /* Receive Enable */
146 #define SCFCR2_TTRG0 0x10 /* Transmit TRiGger 0 */
158 #define FIFO_XMT_TRIGGER_4 0x10
/netbsd-6-1-5-RELEASE/sys/dev/pci/
H A Dcmpcireg.h93 #define CMPCI_REG_INTR_STATUS 0x10
153 # define CMPCI_SB16_SW_LINE_L 0x10
176 # define CMPCI_REG_REVERSE_FR 0x10
186 # define CMPCI_REG_VAUXLM 0x10
202 #define CMPCI_REG_MPU_SIZE 0x10
204 #define CMPCI_REG_FM_SIZE 0x10
H A Dif_tlregs.h34 #define PCI_CBIO 0x10 /* Configuration Base IO Address */
82 #define TL_INT_Areg0 0x10
107 #define TL_LED_ACT 0x10
113 #define TL_NETCOMMAND_CAF 0x10
136 #define TL_NETSIO_EDATA 0x10
145 #define TL_NETSTS_RXSTOP 0x10
/netbsd-6-1-5-RELEASE/sys/arch/mac68k/include/
H A Dviareg.h50 #define DA1O_vOverlay 0x10
62 #define DB1O_vFDesk1 0x10
74 #define DA2I_v2IRQD 0x10
85 #define DB2I_v2TM1A 0x10
177 #define rMonitor 0x10 /* Monitor type */
185 #define RBVMonIDRGB12 0x10 /* 12 inch color */
/netbsd-6-1-5-RELEASE/sys/dev/isa/
H A Dgusreg.h148 #define GUSMASK_IRQ_RESERVED 0x10 /* Reserved (set to 0) */
180 #define GUSMASK_COMBINE 0x10 /* combine Ch 1 IRQ & Ch 2 (MIDI) */
196 #define GUSMASK_DMA_R2 0x10
211 #define GUSMASK_VOICE_BIDIR 0x10 /* Bi-directional looping */
224 #define GUSMASK_VOLUME_BIDIR 0x10 /* Bi-dir volume looping */
264 #define GUS_MAX_RECCHAN16 0x10 /* 0=8bit DMA read, 1=16bit DMA read */
H A Dcmsreg.h80 #define CMS_IREG_OCTAVE_1_0 0x10
89 #define CMS_IREG_FREQ_ENBL4 0x10
110 #define CMS_IREG_NOISE_ENBL4 0x10
/netbsd-6-1-5-RELEASE/sys/arch/hp300/dev/
H A Ddcmreg.h117 } dcm_tfifos[4][0x10]; /* Transmit queues 8ee0 */
159 #define CR_MODM 0x10 /* change modem output lines */
169 #define IIR_SELFT 0x10 /* self test completed */
190 #define LC_6BITS 0x10
211 #define BR_19200 0x10
238 #define RD_BD 0x10
H A Dnhpibreg.h73 #define LIS_APT 0x10
79 #define MIS_BO 0x10
100 #define AUX_CSRE 0x10 /* Clear REN (remote enable) line */
/netbsd-6-1-5-RELEASE/sys/dev/scsipi/
H A Dscsi_tape.h80 #define WRITE_FILEMARKS 0x10
136 u_int8_t pagecode; /* 0x10 */
150 #define SMT_AVC 0x10 /* automatic velocity control */
153 #define SMT_REW 0x10 /* report early warning */
157 #define SMT_EEG 0x10 /* enable EOD generation */
189 #define SMH_DSP_BUFF_MODE_ON 0x10
217 #define QIC_150 0x10
/netbsd-6-1-5-RELEASE/crypto/external/bsd/heimdal/dist/lib/wind/
H A Dgen-errorlist.py92 start = int(m.group(1), 0x10)
93 end = int(m.group(2), 0x10)
99 trans.append([int(m.group(1), 0x10), 1, m.group(2), [t]])
/netbsd-6-1-5-RELEASE/sys/arch/newsmips/dev/
H A Ddmac_0448.h86 #define DM_APAD 0x10
96 #define CH2_INT 0x10
126 # define DMA_INTEN 0x10
/netbsd-6-1-5-RELEASE/sys/arch/macppc/dev/
H A Dpmuvar.h34 #define PMU_POWER_CTRL0 0x10 /* control power of some devices */
81 #define PMU_INT_ADB 0x10 /* ADB autopoll or reply data */
142 PMU_PWR_WAKEUP_RING = 0x10,
/netbsd-6-1-5-RELEASE/sys/dev/mca/
H A Dedcreg.h75 #define CMD_WRITE_ATTACH_BUFF 0x10 /* uses DMA */
95 #define BSR_BUSY 0x10
103 #define ISR_ATTACH_ERR 0x10
/netbsd-6-1-5-RELEASE/sys/arch/evbppc/include/
H A Dwalnut.h106 #define FPGA_SW_SMI 0x10 /* SW_SMI_N present */
131 #define FPGA_BRDC_TC3 0x10 /* DMA_EOT/TC3 is set to TC */
143 #define SW_SEL0 0x10 /* use 405GP arbiter */
/netbsd-6-1-5-RELEASE/sys/arch/arm/footbridge/isa/
H A Dds1687reg.h58 #define RTC_REG_A_DV0 0x10 /* Bank Select */
84 #define RTC_REG_B_UIE 0x10 /* Updated Ended Interrupt Enable */
98 #define RTC_REG_C_UF 0x10 /* Update Ended Flags */

Completed in 162 milliseconds

<<11121314151617181920>>