1/* $NetBSD: cmpcireg.h,v 1.4.16.3 2004/09/21 13:31:01 skrll Exp $ */ 2 3/* 4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Takuya SHIOZAKI <tshiozak@NetBSD.org> . 9 * 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by ITOH Yasufumi. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36/* C-Media CMI8x38 Audio Chip Support */ 37 38#ifndef _DEV_PCI_CMPCIREG_H_ 39#define _DEV_PCI_CMPCIREG_H_ (1) 40 41/* 42 * PCI Configuration Registers 43 */ 44 45#define CMPCI_PCI_IOBASEREG (PCI_MAPREG_START) 46 47 48/* 49 * I/O Space 50 */ 51 52#define CMPCI_REG_FUNC_0 0x00 53# define CMPCI_REG_CH0_DIR 0x00000001 54# define CMPCI_REG_CH1_DIR 0x00000002 55# define CMPCI_REG_CH0_PAUSE 0x00000004 56# define CMPCI_REG_CH1_PAUSE 0x00000008 57# define CMPCI_REG_CH0_ENABLE 0x00010000 58# define CMPCI_REG_CH1_ENABLE 0x00020000 59# define CMPCI_REG_CH0_RESET 0x00040000 60# define CMPCI_REG_CH1_RESET 0x00080000 61 62#define CMPCI_REG_FUNC_1 0x04 63# define CMPCI_REG_JOY_ENABLE 0x00000002 64# define CMPCI_REG_UART_ENABLE 0x00000004 65# define CMPCI_REG_LEGACY_ENABLE 0x00000008 66# define CMPCI_REG_BREQ 0x00000010 67# define CMPCI_REG_MCBINTR_ENABLE 0x00000020 68# define CMPCI_REG_SPDIFOUT_DAC 0x00000040 69# define CMPCI_REG_SPDIF_LOOP 0x00000080 70# define CMPCI_REG_SPDIF0_ENABLE 0x00000100 71# define CMPCI_REG_SPDIF1_ENABLE 0x00000200 72# define CMPCI_REG_DAC_FS_SHIFT 10 73# define CMPCI_REG_DAC_FS_MASK 0x00000007 74# define CMPCI_REG_ADC_FS_SHIFT 13 75# define CMPCI_REG_ADC_FS_MASK 0x00000007 76 77#define CMPCI_REG_CHANNEL_FORMAT 0x08 78# define CMPCI_REG_SPDIN_PHASE 0x80 79# define CMPCI_REG_CH0_FORMAT_SHIFT 0 80# define CMPCI_REG_CH0_FORMAT_MASK 0x00000003 81# define CMPCI_REG_CH1_FORMAT_SHIFT 2 82# define CMPCI_REG_CH1_FORMAT_MASK 0x00000003 83# define CMPCI_REG_FORMAT_MONO 0x00000000 84# define CMPCI_REG_FORMAT_STEREO 0x00000001 85# define CMPCI_REG_FORMAT_8BIT 0x00000000 86# define CMPCI_REG_FORMAT_16BIT 0x00000002 87 88#define CMPCI_REG_INTR_CTRL 0x0c 89# define CMPCI_REG_CH0_INTR_ENABLE 0x00010000 90# define CMPCI_REG_CH1_INTR_ENABLE 0x00020000 91# define CMPCI_REG_TDMA_INTR_ENABLE 0x00040000 92 93#define CMPCI_REG_INTR_STATUS 0x10 94# define CMPCI_REG_CH0_INTR 0x00000001 95# define CMPCI_REG_CH1_INTR 0x00000002 96# define CMPCI_REG_CH0_BUSY 0x00000004 97# define CMPCI_REG_CH1_BUSY 0x00000008 98# define CMPCI_REG_LEGACY_STEREO 0x00000010 99# define CMPCI_REG_LEGACY_HDMA 0x00000020 100# define CMPCI_REG_DMASTAT 0x00000040 101# define CMPCI_REG_XDO46 0x00000080 102# define CMPCI_REG_HTDMA_INTR 0x00004000 103# define CMPCI_REG_LTDMA_INTR 0x00008000 104# define CMPCI_REG_UART_INTR 0x00010000 105# define CMPCI_REG_MCB_INTR 0x04000000 106# define CMPCI_REG_VCO 0x08000000 107# define CMPCI_REG_ANY_INTR 0x80000000 108 109#define CMPCI_REG_LEGACY_CTRL 0x14 110# define CMPCI_REG_LEGACY_SPDIF_ENABLE 0x00200000 111# define CMPCI_REG_SPDIF_COPYRIGHT 0x00400000 112# define CMPCI_REG_XSPDIF_ENABLE 0x00800000 113# define CMPCI_REG_FMSEL_SHIFT 24 114# define CMPCI_REG_FMSEL_MASK 0x00000003 115# define CMPCI_REG_VSBSEL_SHIFT 26 116# define CMPCI_REG_VSBSEL_MASK 0x00000003 117# define CMPCI_REG_VMPUSEL_SHIFT 29 118# define CMPCI_REG_VMPUSEL_MASK 0x00000003 119 120#define CMPCI_REG_MISC 0x18 121# define CMPCI_REG_2ND_SPDIFIN 0x00000100 122# define CMPCI_REG_SPDIFOUT_48K 0x00008000 123# define CMPCI_REG_FM_ENABLE 0x00080000 124# define CMPCI_REG_SPDFLOOPI 0x00100000 125# define CMPCI_REG_SPDIF48K 0x01000000 126# define CMPCI_REG_5V 0x02000000 127# define CMPCI_REG_N4SPK3D 0x04000000 128 129 130#define CMPCI_REG_SBDATA 0x22 131#define CMPCI_REG_SBADDR 0x23 132# define CMPCI_SB16_MIXER_RESET 0x00 133# define CMPCI_SB16_MIXER_MASTER_L 0x30 134# define CMPCI_SB16_MIXER_MASTER_R 0x31 135# define CMPCI_SB16_MIXER_VOICE_L 0x32 136# define CMPCI_SB16_MIXER_VOICE_R 0x33 137# define CMPCI_SB16_MIXER_FM_L 0x34 138# define CMPCI_SB16_MIXER_FM_R 0x35 139# define CMPCI_SB16_MIXER_CDDA_L 0x36 140# define CMPCI_SB16_MIXER_CDDA_R 0x37 141# define CMPCI_SB16_MIXER_LINE_L 0x38 142# define CMPCI_SB16_MIXER_LINE_R 0x39 143# define CMPCI_SB16_MIXER_MIC 0x3A 144# define CMPCI_SB16_MIXER_VALBITS 5 145# define CMPCI_SB16_MIXER_SPEAKER 0x3B 146# define CMPCI_SB16_MIXER_SPEAKER_VALBITS 2 147# define CMPCI_SB16_MIXER_OUTMIX 0x3C 148# define CMPCI_SB16_SW_MIC 0x01 149# define CMPCI_SB16_SW_CD_R 0x02 150# define CMPCI_SB16_SW_CD_L 0x04 151# define CMPCI_SB16_SW_CD (CMPCI_SB16_SW_CD_L|CMPCI_SB16_SW_CD_R) 152# define CMPCI_SB16_SW_LINE_R 0x08 153# define CMPCI_SB16_SW_LINE_L 0x10 154# define CMPCI_SB16_SW_LINE (CMPCI_SB16_SW_LINE_L|CMPCI_SB16_SW_LINE_R) 155# define CMPCI_SB16_SW_FM_R 0x20 156# define CMPCI_SB16_SW_FM_L 0x40 157# define CMPCI_SB16_SW_FM (CMPCI_SB16_SW_FM_L|CMPCI_SB16_SW_FM_R) 158# define CMPCI_SB16_MIXER_ADCMIX_L 0x3D 159# define CMPCI_SB16_MIXER_ADCMIX_R 0x3E 160# define CMPCI_SB16_MIXER_FM_SRC_R 0x20 161# define CMPCI_SB16_MIXER_LINE_SRC_R 0x08 162# define CMPCI_SB16_MIXER_CD_SRC_R 0x02 163# define CMPCI_SB16_MIXER_MIC_SRC 0x01 164# define CMPCI_SB16_MIXER_SRC_R_TO_L(v) ((v) << 1) 165 166# define CMPCI_SB16_MIXER_L_TO_R(addr) ((addr)+1) 167 168# define CMPCI_ADJUST_MIC_GAIN(sc, x) cmpci_adjust((x), 0xf8) 169# define CMPCI_ADJUST_GAIN(sc, x) cmpci_adjust((x), 0xf8) 170# define CMPCI_ADJUST_2_GAIN(sc, x) cmpci_adjust((x), 0xc0) 171 172#define CMPCI_REG_MIXER24 0x24 173# define CMPCI_REG_SPDIN_MONITOR 0x01 174# define CMPCI_REG_SURROUND 0x02 175# define CMPCI_REG_INDIVIDUAL 0x20 176# define CMPCI_REG_REVERSE_FR 0x10 177# define CMPCI_REG_FMMUTE 0x80 178# define CMPCI_REG_WSMUTE 0x40 179# define CMPCI_REG_WAVEINL 0x08 180# define CMPCI_REG_WAVEINR 0x04 181 182#define CMPCI_REG_MIXER25 0x25 183# define CMPCI_REG_RAUXREN 0x80 184# define CMPCI_REG_RAUXLEN 0x40 185# define CMPCI_REG_VAUXRM 0x20 /* 0: mute, 1: unmute */ 186# define CMPCI_REG_VAUXLM 0x10 187# define CMPCI_REG_VADMIC 0x0E 188# define CMPCI_REG_MICGAINZ 0x01 /* 1: disable preamp */ 189 190# define CMPCI_ADJUST_ADMIC_GAIN(sc, x) (cmpci_adjust((x), 0xe0) >> 5) 191# define CMPCI_REG_ADMIC_VALBITS 3 192# define CMPCI_REG_ADMIC_MASK 0x07 193# define CMPCI_REG_ADMIC_SHIFT 0x01 194 195/* Note that the doc tells a lie */ 196#define CMPCI_REG_MIXER_AUX 0x26 197# define CMPCI_ADJUST_AUX_GAIN(sc, l, r) \ 198 (cmpci_adjust((l), 0xc0) >> 4 | cmpci_adjust((r), 0xc0)) 199# define CMPCI_REG_AUX_VALBITS 4 200 201#define CMPCI_REG_MPU_BASE 0x40 202#define CMPCI_REG_MPU_SIZE 0x10 203#define CMPCI_REG_FM_BASE 0x50 204#define CMPCI_REG_FM_SIZE 0x10 205 206#define CMPCI_REG_DMA0_BASE 0x80 207#define CMPCI_REG_DMA0_BYTES 0x84 208#define CMPCI_REG_DMA0_SAMPLES 0x86 209#define CMPCI_REG_DMA1_BASE 0x88 210#define CMPCI_REG_DMA1_BYTES 0x8C 211#define CMPCI_REG_DMA1_SAMPLES 0x8E 212 213 214/* sample rate */ 215#define CMPCI_REG_RATE_5512 0 216#define CMPCI_REG_RATE_11025 1 217#define CMPCI_REG_RATE_22050 2 218#define CMPCI_REG_RATE_44100 3 219#define CMPCI_REG_RATE_8000 4 220#define CMPCI_REG_RATE_16000 5 221#define CMPCI_REG_RATE_32000 6 222#define CMPCI_REG_RATE_48000 7 223#define CMPCI_REG_NUMRATE 8 224 225#endif /* _DEV_PCI_CMPCIREG_H_ */ 226 227/* end of file */ 228