Searched refs:bit (Results 26 - 46 of 46) sorted by relevance

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/macosx-10.5.8/xnu-1228.15.4/osfmk/ppc/
H A Daligned_data.s84 EXT(GratefulDebWork): ; Enough for 2 rows of 8 chars of 16-pixel wide 32-bit pixels and a 256 byte work area
H A Dhibernate_restore.s113 mtmsrd r9 ; turn 64-bit addressing on
174 mtmsrd r9 ; turn 64-bit mode off
H A Dlowmem_vectors.s70 ; Some machines (so far, 32-bit guys) will always ignore a non-START interrupt.
110 rlwinm. r13,r13,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
113 bne-- rxIg64 ; 64-bit path...
152 LEXT(extPatchMCK) ; This is patched to a nop for 64-bit
153 b h200aaa ; Skip 64-bit code...
351 ; 8-bit index into the "scTable", and dispatch on it to handle the Ultra
368 cntlzw r13,r13 ; set bit 0x20 iff a 0x7FFx trap
369 cntlzw r11,r11 ; set bit 0x20 iff a 0xFFFFFFF8 trap
370 xoris r0,r0,0x8000 ; Flip bit to make 0 iff 0x80000000
371 rlwimi r11,r13,31,0x10 ; move 0x7FFx bit int
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H A Dstart.s92 mtmsrd r12 ; Make sure we are in 32-bit mode
104 rlwimi r30,r28,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
260 ori r17,r17,lo16(pfValid) ; Set the valid bit
263 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
266 bne++ start64 ; Skip following if 64-bit...
388 vspltish v1,1 ; Turn on the non-Java bit and saturate
389 vspltisw v0,1 ; Turn on the saturate bit
446 rlwinm. r0,r17,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
447 beq++ isnot64 ; Skip following if not 64-bit...
450 rldicl r29,r29,0,MSR_SF_BIT+1 ; turn 64-bit mod
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H A Dhw_lock.s111 * unsigned int hw_lock_bit(hw_lock_t, unsigned int bit, unsigned int timeout)
113 * Try to acquire spin-lock. The second parameter is the bit mask to test and set.
123 mr r12,r4 ; Load bit mask
140 li r12,ILK_LOCKED ; Load bit mask
146 li r12,ILK_LOCKED ; Load bit mask
166 li r12,ILK_LOCKED ; Load bit mask
201 ori r7,r0,lo16(MASK(MSR_EE)) ; Get EE bit on too
278 * unsigned int hw_unlock_bit(hw_lock_t, unsigned int bit)
280 * Release bit based spin-lock. The second parameter is the bit mas
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H A DEmulate.s72 bf-- pf64Bitb,emn64 ; Skip if not 64-bit
73 b EXT(Emulate64) ; Jump to the 64-bit code...
102 rlwimi r20,r10,8,17,17 ; Move bit 25 to bit 17
105 rlwimi r20,r10,3,18,21 ; Move bit 21-24 to bit 18-21
168 or r3,r23,r3 ; Turn on the DR and RI bit if translation was on
192 oris r4,r4,hi16(SAVredrive) ; Set the redrive bit
222 bf-- pf64Bitb,aan64 ; Skip if not 64-bit
223 b EXT(AlignAssist64) ; Jump to the 64-bit cod
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H A DFirmware.s93 rlwinm r1,r0,2,1,29 /* Clear out bit 0 and multiply by 4 */
197 li r8,lo16(MASK(MSR_DR)) ; Get the DR bit
198 rlwinm. r9,r9,0,pf64Bitb,pf64Bitb ; Are we 64-bit?
199 ori r8,r8,lo16(MASK(MSR_EE)) ; Add in the EE bit
204 rldimi r8,r7,63,MSR_SF_BIT ; Set SF bit (bit 0)
205 sldi r3,r3,32 ; Slide on over for true 64-bit address
229 bt-- cr0_eq,rr32b ; We are not 64-bit...
474 li r7,0x44 /* x16 clock, 1 stop bit */
502 li r7,0xE2 /* DTR mode, 8bit/cha
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H A Dhw_exception.s421 ori r11,r11,lo16(MASK(MSR_EE)) ; Turn on interruption enabled bit
556 rlwinm. r0,r0,0,MSR_SF_BIT,MSR_SF_BIT ; Test for 64 bit caller
557 lwz r0,MACH_TRAP_ARG_MUNGE32(r31) ; Pick up the 32 bit munge function address
559 lwz r0,MACH_TRAP_ARG_MUNGE64(r31) ; Pick up the 64 bit munge function address
621 rlwinm. r0,r0,0,MSR_SF_BIT,MSR_SF_BIT ; Test for 64 bit caller
622 lwz r0,MACH_TRAP_ARG_MUNGE32(r31) ; Pick up the 32 bit munge function address
624 lwz r0,MACH_TRAP_ARG_MUNGE64(r31) ; Pick up the 64 bit munge function address
1058 andc r7,r7,r11 ; Remove the stack reset bit in case we pass this one
1440 oris r18,r18,hi16(umwSwitchAway) ; Set the switch-away bit in case we go to user
1478 cmplw r13,r24 ; Is this earlier than the decrementer? (logical compare takes care of high bit o
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H A Dcswtch.s71 oris r10,r10,hi16(OnProc) /* Set OnProc bit */
335 * R3 = switcher's savearea (32-bit virtual)
355 rlwinm. r0,r0,0,pf64Bitb,pf64Bitb ; Check for 64-bit
366 bne++ siSixtyFour ; Go do 64-bit...
388 li r12,lo16(MASK(MSR_EE)) ; Get the EE bit
1724 vspltish v1,1 ; Turn on the non-Java bit and saturate
1725 vspltisw v0,1 ; Turn on the saturate bit
2043 ; r8 = bitmask with bit n set (for even n) if either of that pair of VRs is in use
2187 bt-- pf32Byteb,vr_ld0 ; skip if 32-bit processor
2220 // r5 = 1st bit i
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/macosx-10.5.8/xnu-1228.15.4/osfmk/i386/
H A Dmp.h238 #define i_bit(bit, word) ((long)(*(word)) & ((long)1 << (bit)))
H A Dcpuid.c51 #define bit(n) (1UL << (n)) macro
52 #define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
379 /* Fold in the Invariant TSC feature bit, if present */
H A Dcpu_threads.c48 #define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
/macosx-10.5.8/xnu-1228.15.4/bsd/ufs/ffs/
H A Dffs_alloc.c1094 int i, got, run, bno, bit, map; local
1165 bit = 1 << (bpref % NBBY);
1167 if ((map & bit) == 0) {
1175 bit <<= 1;
1178 bit = 1;
1600 * map for an appropriate bit pattern
1657 int i, start, end, forw, back, map, bit; local
1679 bit = 1 << (start % NBBY);
1681 if ((map & bit) == 0)
1684 bit <<
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/macosx-10.5.8/xnu-1228.15.4/osfmk/chud/ppc/
H A Dchud_cpu_asm.s46 ;; generic PPC 64-bit wide SPRs
68 ;; GPUL specific 64-bit wide SPRs
297 ;; generic PPC 64-bit wide SPRs
319 ;; GPUL specific 64-bit wide SPRs
/macosx-10.5.8/xnu-1228.15.4/osfmk/ddb/
H A Dmakedis.c78 the function. Each character of the string represents one bit,
79 with the least significant bit being the last. A character can be
97 case where its first argument contains matching values in those bit
107 two such lines to specify exactly the same constant bit values. But
108 it is allowed for a line to have all the same constant bit values as
124 shifted as if that bitfield were in the least-significant bit
125 position. Thus, a single-bit field always has value 0 or 1.
163 microprocessor. This processor has 8-bit opcodes which are
201 on the value of the argument, which is assumed to be a three-bit
314 /* componentbits has a 1 bit fo
708 char bit; local
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/macosx-10.5.8/xnu-1228.15.4/bsd/dev/ppc/
H A Dfasttrap_isa.c112 * we bail. Otherwise we have a bit more to do.
181 /* 64-bit */
185 /* 32-bit */
224 testr2 = tp->ftt_bi = (uint8_t)((instr >> (31 - 15)) & 0x1F); /* Extract condition register bit */
390 if(sv->save_srr1 & 0x8000000000000000ULL) { /* Are we running in 64-bit? */
395 argv[i] = (uint64_t)farg; /* Convert to 64-bit */
420 if(sv->save_srr1 & 0x8000000000000000ULL) addrmask = 0xFFFFFFFFFFFFFFFFULL; /* Set 64-bit addressing if enabled */
421 else addrmask = 0x00000000FFFFFFFFULL; /* Otherwise set 32-bit */
641 if(!(sv->save_srr1 & 0x8000000000000000ULL)) npc &= 0x00000000FFFFFFFF; /* Wrap new PC if running 32-bit */
672 if(!(bo & 4)) { /* Skip the next bit i
689 int32_t curdcd, lastmask, newmask, spr, bit, bito, word; local
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/macosx-10.5.8/xnu-1228.15.4/osfmk/ipc/
H A Dipc_kmsg.c1654 /* out of line descriptors differ in size between 32 and 64 bit processes */
2366 * copyout of the reply port is a bit tricky. If there was
3266 mach_msg_bits_t bit);
3349 mach_msg_bits_t bit)
3351 switch (bit) {
3366 unsigned int bit, i; local
3381 for (i = 0, bit = 1; i < sizeof(mbits) * 8; ++i, bit <<= 1) {
3382 if ((mbits & bit) == 0)
3384 bit_name = msgh_bit_decode((mach_msg_bits_t)bit);
3348 msgh_bit_decode( mach_msg_bits_t bit) argument
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/macosx-10.5.8/xnu-1228.15.4/iokit/Kernel/
H A DIOPlatformExpert.cpp405 UInt32 bit = 1 << (absevent & 0x1f); local
407 && (sStartStopBitField[absevent >> 5] & bit) ) {
/macosx-10.5.8/xnu-1228.15.4/bsd/netinet/
H A Dip_output.c2001 #define OPTSET(bit) \
2003 inp->inp_flags |= bit; \
2005 inp->inp_flags &= ~bit;
2257 #define OPTBIT(bit) (inp->inp_flags & bit ? 1 : 0)
/macosx-10.5.8/xnu-1228.15.4/bsd/netinet6/
H A Dip6_output.c1449 #define OPTSET(bit) \
1452 in6p->in6p_flags |= (bit); \
1454 in6p->in6p_flags &= ~(bit); \
1456 #define OPTBIT(bit) (in6p->in6p_flags & (bit) ? 1 : 0)
/macosx-10.5.8/xnu-1228.15.4/bsd/vfs/
H A Dvfs_cluster.c183 * can represent it in a 32 bit int
1822 * chunk sizes that fit in a 32 bit int
3023 * so that we correctly deal with a change in state of the hardware modify bit...
3080 * chunk sizes that fit in a 32 bit int
4214 * chunk sizes that fit in a 32 bit int
4762 * - the hardware dirty bit is cleared when the page is gathered into the UPL... the software dirty bit is set
4763 * - if we have to abort the I/O for some reason, the software dirty bit is left set since we didn't clean the page
4764 * - when we commit the page, the software dirty bit is cleared... the hardware dirty bit i
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