Lines Matching refs:bit
70 ; Some machines (so far, 32-bit guys) will always ignore a non-START interrupt.
110 rlwinm. r13,r13,0,pf64Bitb,pf64Bitb ; Is this a 64-bit machine?
113 bne-- rxIg64 ; 64-bit path...
152 LEXT(extPatchMCK) ; This is patched to a nop for 64-bit
153 b h200aaa ; Skip 64-bit code...
351 ; 8-bit index into the "scTable", and dispatch on it to handle the Ultra
368 cntlzw r13,r13 ; set bit 0x20 iff a 0x7FFx trap
369 cntlzw r11,r11 ; set bit 0x20 iff a 0xFFFFFFF8 trap
370 xoris r0,r0,0x8000 ; Flip bit to make 0 iff 0x80000000
371 rlwimi r11,r13,31,0x10 ; move 0x7FFx bit into position
372 cntlzw r13,r0 ; Set bit 0x20 iff 0x80000000
373 xoris r0,r0,0x8000 ; Flip bit to restore R0
374 rlwimi r11,r13,2,0x80 ; Set bit 0x80 iff CutTrace
377 cntlzw r13,r13 ; set bit 0x20 iff 0x6004
378 rlwinm r11,r11,0,0,30 ; clear out bit 31
379 rlwimi r11,r13,1,0x40 ; move 0x6004 bit into position
541 ; Thermal interruption - 64-bit
607 * 0x00007FF2 - User state only - thread info (32-bit mode)
609 * 0x00007FF4 - Kernel only - loadMSR - not used on 64-bit machines
612 * "scTable" is an array of 2-byte addresses, accessed using a 7-bit index derived from the syscall
778 * with interrupts and VM off, in 64-bit mode if supported, and with all registers live
826 lwz r3,UAW+4(r11) ; get user assist word, assuming a 32-bit processor
828 ld r3,UAW(r11) ; get the whole doubleword if 64-bit (patched to nop if 32-bit)
841 ; Handle "Load MSR" UFT (0x7FF4). This is not used on 64-bit processors, though it would work.
864 b uftX64 ; patched to NOP if 32-bit processor
897 b uftct64 ; patched to NOP if 32-bit processor
903 rlwinm r20,r20,MSR_PR_BIT-enaUsrFCallb,MASK(MSR_PR) ; Shift the validity bit over to pr bit spot
909 andi. r20,r20,MASK(MSR_PR) ; Set cr0_eq is we are in problem state and the validity bit is not set
917 rlwnm r24,r23,r24,12,12 ; Shift cpu mask bit to rupt type mask
1034 ; This is the 64-bit version.
1041 rlwinm r20,r20,MSR_PR_BIT-enaUsrFCallb,MASK(MSR_PR) ; Shift the validity bit over to pr bit spot
1047 andi. r20,r20,MASK(MSR_PR) ; Set cr0_eq when we are in problem state and the validity bit is not set
1054 rlwnm r24,r23,r24,12,12 ; Shift cpu mask bit to rupt type mask
1150 b extEntry64 ; Go straight to the 64-bit code...
1177 * ENTRY: interrupts off, VM off, in 64-bit mode if supported
1204 b extEntry64 ; Go do 64-bit (patched to a nop if 32-bit)
1237 ; This is the 32-bit context saving stuff
1256 andi. r1,r11,T_FAM ; Check FAM bit
1260 andc r11,r11,r1 ; Clear FAM bit
1272 srw r1,r3,r1 ; Set bit for current exception
1462 rlwnm r7,r25,r22,22,22 ; Set CR5_EQ bit position to 0 if tracing allowed
1464 srw r26,r26,r19 ; Get bit position of cpu number
1586 ; This is the 64-bit context saving stuff
1606 slw r0,r0,r2 ; Move transform validity bit to bit 0
1624 xor r11,r11,r4 ; Transform 970 rupt code to standard keeping FAM bit
1641 andi. r1,r11,T_FAM ; Check FAM bit
1644 andc r11,r11,r1 ; Clear FAM bit
1655 srw r1,r3,r1 ; Set bit for current exception
1795 rlwnm r7,r25,r22,22,22 ; Set CR5_EQ bit position to 0 if tracing allowed
1796 srw r26,r26,r19 ; Get bit position of cpu number
1935 vspltish v1,1 ; Turn on the non-Java bit and saturate
1937 vspltisw v0,1 ; Turn on the saturate bit
2059 rlwinm r6,r0,1,0,31 ; Move sign bit to the end
2288 srw r1,r5,r1 ; Set bit for current exception
2294 NoFamPf: andi. r4,r0,lo16(MASK(MSR_RI)) ; See if the recover bit is on
2336 andc r30,r13,r0 ; Round down to page boundary (64-bit safe)
2338 bf-- pf64Bitb,xcswNo64 ; Not 64-bit...
2411 ; 64-bit machine checks
2422 lwz r21,savedsisr(r13) ; We might need this in a bit
2423 ld r22,savedar(r13) ; We might need this in a bit
2513 ; Also note that we will lose bit 63
2558 andis. r0,r6,0x0800 ; See if valid bit is on
2583 rldicr r7,r7,0,35 ; Clear the valid bit and the rest
2633 ; dig a bit further.
2730 lis r0,0x0080 ; Get a 0x0080 (bit 9 >> 32)
2732 sldi r0,r0,32 ; Get the "forced ICBI match" bit
2856 rlwimi r5,r5,15,31,31 ; Scoot trap flag down to a spare bit
2860 rlwimi. r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits and see if ijsave is 0
2862 crandc cr0_eq,cr1_eq,cr0_eq ; If we are injecting, ijsave will be non-zero and we had the trap bit set
2880 rlwimi r7,r4,0,MSR_FP_BIT,MSR_FP_BIT ; Make sure we retain the current floating point enable bit
2895 * into a different one. Thus we clear the redrive bit.
2966 rlwimi. r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits and see if ijsave is 0
2976 rlwimi r4,r5,0,MSR_FP_BIT,MSR_FP_BIT ; Copy the new FP enable bit into the old SRR1
3008 rlwinm r4,r4,0,0,31 ; Clean top half of virtual savearea if 64-bit
3018 bt++ pf64Bitb,puLaunch ; Handle 64-bit machine...
3030 * properly on a 64-bit machine) we use holdQFret to indicate that the list
3055 bt++ pf64Bitb,eat64a ; Skip down to the 64-bit version of this
3058 ; This starts the 32-bit version
3327 ; This starts the 64-bit version
3587 bt++ pf64Bitb,eeSixtyFour ; We are 64-bit...
3601 rldimi r30,r0,63,MSR_SF_BIT ; Set SF bit (bit 0)
3602 mtmsrd r30 ; Set 64-bit mode, turn off EE, DR, and IR