| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 1455 MachineRegisterInfo *MRI; member in struct:__anon10136::ARMPreAllocLoadStoreOpt
1485 MRI = &Fn.getRegInfo();
1739 MRI->constrainRegClass(EvenReg, TRC);
1740 MRI->constrainRegClass(OddReg, TRC);
1776 MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg);
1777 MRI->setRegAllocationHint(OddReg, ARMRI::RegPairOdd, EvenReg);
|
| H A D | ARMFrameLowering.cpp | 1176 MachineRegisterInfo &MRI = MF.getRegInfo();
1179 if (!MRI.isPhysRegOrOverlapUsed(ARM::D8 + NumSpills))
|
| H A D | ARMFastISel.cpp | 2144 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2152 MRI.addLiveOut(VA.getLocReg());
2833 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/ |
| H A D | NVPTXAsmPrinter.cpp | 370 MRI = &MF->getRegInfo();
454 const TargetRegisterClass * RC = MRI->getRegClass(vr);
1605 unsigned int numVRs = MRI->getNumVirtRegs();
1608 const TargetRegisterClass *RC = MRI->getRegClass(vr);
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1507 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); local
1509 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1510 MRI.addLiveOut(RVLocs[i].getLocReg());
1601 MRI.addLiveOut(X86::RAX);
2668 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2676 MachineInstr *Def = MRI->getVRegDef(VR);
2866 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local
2877 MFI, MRI, TII))
9537 MachineRegisterInfo &MRI = MF.getRegInfo(); local
9553 unsigned Vreg = MRI
2667 MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const X86InstrInfo *TII) argument
12087 MachineRegisterInfo &MRI = MF->getRegInfo(); local
12319 MachineRegisterInfo &MRI = MF->getRegInfo(); local
12624 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local
13056 MachineRegisterInfo &MRI = MF->getRegInfo(); local
[all...] |
| H A D | X86FastISel.cpp | 802 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
810 MRI.addLiveOut(VA.getLocReg());
823 MRI.addLiveOut(X86::RAX);
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/MC/ |
| H A D | MCAsmStreamer.cpp | 901 const MCRegisterInfo &MRI = getContext().getRegisterInfo(); local
902 unsigned LLVMRegister = MRI.getLLVMRegNum(Register, true);
|
| /macosx-10.10.1/llvmCore-3425.0.34/tools/llvm-objdump/ |
| H A D | MachODump.cpp | 261 OwningPtr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
265 *MRI, *STI));
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 47 const MCRegisterInfo *MRI; member in class:__anon10142::ARMAsmParser
245 MRI = &getContext().getRegisterInfo();
2909 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2936 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2942 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3068 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3074 Reg = MRI
[all...] |
| /macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/ |
| H A D | BranchFolding.cpp | 189 MachineRegisterInfo &MRI = MF.getRegInfo(); local
190 if (MRI.tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
193 MRI.invalidateLiveness();
|
| H A D | IfConversion.cpp | 158 MachineRegisterInfo *MRI; member in class:__anon9949::IfConverter
268 MRI = &MF.getRegInfo();
272 PreRegAlloc = MRI->isSSA();
|
| H A D | ScheduleDAG.cpp | 40 MF(mf), MRI(mf.getRegInfo()),
|
| /macosx-10.10.1/llvmCore-3425.0.34/include/llvm/CodeGen/ |
| H A D | ScheduleDAG.h | 523 MachineRegisterInfo &MRI; // Virtual/real register map member in class:llvm::ScheduleDAG
|
| /macosx-10.10.1/screen-22/screen/ |
| H A D | tty.c | 1472 #if defined(MRI)
1473 # define TIOCM_RNG MRI
1474 #endif /* MRI */
|
| H A D | tty.c.dist | 1472 #if defined(MRI)
1473 # define TIOCM_RNG MRI
1474 #endif /* MRI */
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGISel.cpp | 460 MachineRegisterInfo &MRI = MF->getRegInfo(); local
474 MRI.replaceRegWith(From, To);
480 MRI.freezeReservedRegs(*MF);
|
| H A D | ScheduleDAGSDNodes.cpp | 782 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
|
| H A D | SelectionDAGBuilder.cpp | 827 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); local
828 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 142 const MCRegisterInfo &MRI,
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 341 const MCRegisterInfo &MRI,
340 createARMMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
|