1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ARMMCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mccodeemitter" 15#include "MCTargetDesc/ARMAddressingModes.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "MCTargetDesc/ARMFixupKinds.h" 18#include "MCTargetDesc/ARMMCExpr.h" 19#include "MCTargetDesc/ARMMCTargetDesc.h" 20#include "llvm/MC/MCCodeEmitter.h" 21#include "llvm/MC/MCContext.h" 22#include "llvm/MC/MCExpr.h" 23#include "llvm/MC/MCInst.h" 24#include "llvm/MC/MCInstrInfo.h" 25#include "llvm/MC/MCRegisterInfo.h" 26#include "llvm/MC/MCSubtargetInfo.h" 27#include "llvm/ADT/APFloat.h" 28#include "llvm/ADT/Statistic.h" 29#include "llvm/Support/raw_ostream.h" 30 31using namespace llvm; 32 33STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); 34STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created."); 35 36namespace { 37class ARMMCCodeEmitter : public MCCodeEmitter { 38 ARMMCCodeEmitter(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION; 39 void operator=(const ARMMCCodeEmitter &) LLVM_DELETED_FUNCTION; 40 const MCInstrInfo &MCII; 41 const MCSubtargetInfo &STI; 42 const MCContext &CTX; 43 44public: 45 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 46 MCContext &ctx) 47 : MCII(mcii), STI(sti), CTX(ctx) { 48 } 49 50 ~ARMMCCodeEmitter() {} 51 52 bool isThumb() const { 53 // FIXME: Can tablegen auto-generate this? 54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 55 } 56 bool isThumb2() const { 57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0; 58 } 59 bool isTargetDarwin() const { 60 Triple TT(STI.getTargetTriple()); 61 Triple::OSType OS = TT.getOS(); 62 return OS == Triple::Darwin || OS == Triple::MacOSX || OS == Triple::IOS; 63 } 64 65 unsigned getMachineSoImmOpValue(unsigned SoImm) const; 66 67 // getBinaryCodeForInstr - TableGen'erated function for getting the 68 // binary encoding for an instruction. 69 uint64_t getBinaryCodeForInstr(const MCInst &MI, 70 SmallVectorImpl<MCFixup> &Fixups) const; 71 72 /// getMachineOpValue - Return binary encoding of operand. If the machine 73 /// operand requires relocation, record the relocation and return zero. 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 75 SmallVectorImpl<MCFixup> &Fixups) const; 76 77 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of 78 /// the specified operand. This is used for operands with :lower16: and 79 /// :upper16: prefixes. 80 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 81 SmallVectorImpl<MCFixup> &Fixups) const; 82 83 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 84 unsigned &Reg, unsigned &Imm, 85 SmallVectorImpl<MCFixup> &Fixups) const; 86 87 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate 88 /// BL branch target. 89 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 90 SmallVectorImpl<MCFixup> &Fixups) const; 91 92 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 93 /// BLX branch target. 94 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 95 SmallVectorImpl<MCFixup> &Fixups) const; 96 97 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 98 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 99 SmallVectorImpl<MCFixup> &Fixups) const; 100 101 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 102 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 103 SmallVectorImpl<MCFixup> &Fixups) const; 104 105 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 106 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 107 SmallVectorImpl<MCFixup> &Fixups) const; 108 109 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate 110 /// branch target. 111 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 112 SmallVectorImpl<MCFixup> &Fixups) const; 113 114 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 115 /// immediate Thumb2 direct branch target. 116 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 117 SmallVectorImpl<MCFixup> &Fixups) const; 118 119 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate 120 /// branch target. 121 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 122 SmallVectorImpl<MCFixup> &Fixups) const; 123 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 124 SmallVectorImpl<MCFixup> &Fixups) const; 125 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 126 SmallVectorImpl<MCFixup> &Fixups) const; 127 128 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate 129 /// ADR label target. 130 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 131 SmallVectorImpl<MCFixup> &Fixups) const; 132 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 133 SmallVectorImpl<MCFixup> &Fixups) const; 134 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 135 SmallVectorImpl<MCFixup> &Fixups) const; 136 137 138 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 139 /// operand. 140 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 141 SmallVectorImpl<MCFixup> &Fixups) const; 142 143 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 144 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 145 SmallVectorImpl<MCFixup> &Fixups)const; 146 147 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 148 /// operand. 149 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 150 SmallVectorImpl<MCFixup> &Fixups) const; 151 152 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 153 /// operand. 154 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 155 SmallVectorImpl<MCFixup> &Fixups) const; 156 157 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' 158 /// operand. 159 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 160 SmallVectorImpl<MCFixup> &Fixups) const; 161 162 163 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 164 /// operand as needed by load/store instructions. 165 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 166 SmallVectorImpl<MCFixup> &Fixups) const; 167 168 /// getLdStmModeOpValue - Return encoding for load/store multiple mode. 169 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, 170 SmallVectorImpl<MCFixup> &Fixups) const { 171 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 172 switch (Mode) { 173 default: llvm_unreachable("Unknown addressing sub-mode!"); 174 case ARM_AM::da: return 0; 175 case ARM_AM::ia: return 1; 176 case ARM_AM::db: return 2; 177 case ARM_AM::ib: return 3; 178 } 179 } 180 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 181 /// 182 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 183 switch (ShOpc) { 184 case ARM_AM::no_shift: 185 case ARM_AM::lsl: return 0; 186 case ARM_AM::lsr: return 1; 187 case ARM_AM::asr: return 2; 188 case ARM_AM::ror: 189 case ARM_AM::rrx: return 3; 190 } 191 llvm_unreachable("Invalid ShiftOpc!"); 192 } 193 194 /// getAddrMode2OpValue - Return encoding for addrmode2 operands. 195 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 196 SmallVectorImpl<MCFixup> &Fixups) const; 197 198 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. 199 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 200 SmallVectorImpl<MCFixup> &Fixups) const; 201 202 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. 203 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 204 SmallVectorImpl<MCFixup> &Fixups) const; 205 206 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. 207 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 208 SmallVectorImpl<MCFixup> &Fixups) const; 209 210 /// getAddrMode3OpValue - Return encoding for addrmode3 operands. 211 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 212 SmallVectorImpl<MCFixup> &Fixups) const; 213 214 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 215 /// operand. 216 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 217 SmallVectorImpl<MCFixup> &Fixups) const; 218 219 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 220 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 221 SmallVectorImpl<MCFixup> &Fixups) const; 222 223 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 224 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 225 SmallVectorImpl<MCFixup> &Fixups) const; 226 227 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. 228 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 229 SmallVectorImpl<MCFixup> &Fixups) const; 230 231 /// getCCOutOpValue - Return encoding of the 's' bit. 232 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, 233 SmallVectorImpl<MCFixup> &Fixups) const { 234 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or 235 // '1' respectively. 236 return MI.getOperand(Op).getReg() == ARM::CPSR; 237 } 238 239 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. 240 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, 241 SmallVectorImpl<MCFixup> &Fixups) const { 242 unsigned SoImm = MI.getOperand(Op).getImm(); 243 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 244 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 245 246 // Encode rotate_imm. 247 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 248 << ARMII::SoRotImmShift; 249 250 // Encode immed_8. 251 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 252 return Binary; 253 } 254 255 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. 256 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, 257 SmallVectorImpl<MCFixup> &Fixups) const { 258 unsigned SoImm = MI.getOperand(Op).getImm(); 259 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); 260 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); 261 return Encoded; 262 } 263 264 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 265 SmallVectorImpl<MCFixup> &Fixups) const; 266 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 267 SmallVectorImpl<MCFixup> &Fixups) const; 268 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 269 SmallVectorImpl<MCFixup> &Fixups) const; 270 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 271 SmallVectorImpl<MCFixup> &Fixups) const; 272 273 /// getSORegOpValue - Return an encoded so_reg shifted register value. 274 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, 275 SmallVectorImpl<MCFixup> &Fixups) const; 276 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, 277 SmallVectorImpl<MCFixup> &Fixups) const; 278 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, 279 SmallVectorImpl<MCFixup> &Fixups) const; 280 281 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, 282 SmallVectorImpl<MCFixup> &Fixups) const { 283 return 64 - MI.getOperand(Op).getImm(); 284 } 285 286 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 287 SmallVectorImpl<MCFixup> &Fixups) const; 288 289 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, 290 SmallVectorImpl<MCFixup> &Fixups) const; 291 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 292 SmallVectorImpl<MCFixup> &Fixups) const; 293 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 294 SmallVectorImpl<MCFixup> &Fixups) const; 295 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 296 SmallVectorImpl<MCFixup> &Fixups) const; 297 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 298 SmallVectorImpl<MCFixup> &Fixups) const; 299 300 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, 301 SmallVectorImpl<MCFixup> &Fixups) const; 302 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, 303 SmallVectorImpl<MCFixup> &Fixups) const; 304 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, 305 SmallVectorImpl<MCFixup> &Fixups) const; 306 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, 307 SmallVectorImpl<MCFixup> &Fixups) const; 308 309 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, 310 SmallVectorImpl<MCFixup> &Fixups) const; 311 312 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, 313 unsigned EncodedValue) const; 314 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, 315 unsigned EncodedValue) const; 316 unsigned NEONThumb2DupPostEncoder(const MCInst &MI, 317 unsigned EncodedValue) const; 318 319 unsigned VFPThumb2PostEncoder(const MCInst &MI, 320 unsigned EncodedValue) const; 321 322 void EmitByte(unsigned char C, raw_ostream &OS) const { 323 OS << (char)C; 324 } 325 326 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const { 327 // Output the constant in little endian byte order. 328 for (unsigned i = 0; i != Size; ++i) { 329 EmitByte(Val & 255, OS); 330 Val >>= 8; 331 } 332 } 333 334 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 335 SmallVectorImpl<MCFixup> &Fixups) const; 336}; 337 338} // end anonymous namespace 339 340MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII, 341 const MCRegisterInfo &MRI, 342 const MCSubtargetInfo &STI, 343 MCContext &Ctx) { 344 return new ARMMCCodeEmitter(MCII, STI, Ctx); 345} 346 347/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing 348/// instructions, and rewrite them to their Thumb2 form if we are currently in 349/// Thumb2 mode. 350unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, 351 unsigned EncodedValue) const { 352 if (isThumb2()) { 353 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved 354 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are 355 // set to 1111. 356 unsigned Bit24 = EncodedValue & 0x01000000; 357 unsigned Bit28 = Bit24 << 4; 358 EncodedValue &= 0xEFFFFFFF; 359 EncodedValue |= Bit28; 360 EncodedValue |= 0x0F000000; 361 } 362 363 return EncodedValue; 364} 365 366/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store 367/// instructions, and rewrite them to their Thumb2 form if we are currently in 368/// Thumb2 mode. 369unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, 370 unsigned EncodedValue) const { 371 if (isThumb2()) { 372 EncodedValue &= 0xF0FFFFFF; 373 EncodedValue |= 0x09000000; 374 } 375 376 return EncodedValue; 377} 378 379/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup 380/// instructions, and rewrite them to their Thumb2 form if we are currently in 381/// Thumb2 mode. 382unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, 383 unsigned EncodedValue) const { 384 if (isThumb2()) { 385 EncodedValue &= 0x00FFFFFF; 386 EncodedValue |= 0xEE000000; 387 } 388 389 return EncodedValue; 390} 391 392/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite 393/// them to their Thumb2 form if we are currently in Thumb2 mode. 394unsigned ARMMCCodeEmitter:: 395VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const { 396 if (isThumb2()) { 397 EncodedValue &= 0x0FFFFFFF; 398 EncodedValue |= 0xE0000000; 399 } 400 return EncodedValue; 401} 402 403/// getMachineOpValue - Return binary encoding of operand. If the machine 404/// operand requires relocation, record the relocation and return zero. 405unsigned ARMMCCodeEmitter:: 406getMachineOpValue(const MCInst &MI, const MCOperand &MO, 407 SmallVectorImpl<MCFixup> &Fixups) const { 408 if (MO.isReg()) { 409 unsigned Reg = MO.getReg(); 410 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg); 411 412 // Q registers are encoded as 2x their register number. 413 switch (Reg) { 414 default: 415 return RegNo; 416 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: 417 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: 418 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: 419 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: 420 return 2 * RegNo; 421 } 422 } else if (MO.isImm()) { 423 return static_cast<unsigned>(MO.getImm()); 424 } else if (MO.isFPImm()) { 425 return static_cast<unsigned>(APFloat(MO.getFPImm()) 426 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 427 } 428 429 llvm_unreachable("Unable to encode MCOperand!"); 430} 431 432/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. 433bool ARMMCCodeEmitter:: 434EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, 435 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const { 436 const MCOperand &MO = MI.getOperand(OpIdx); 437 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 438 439 Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 440 441 int32_t SImm = MO1.getImm(); 442 bool isAdd = true; 443 444 // Special value for #-0 445 if (SImm == INT32_MIN) { 446 SImm = 0; 447 isAdd = false; 448 } 449 450 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 451 if (SImm < 0) { 452 SImm = -SImm; 453 isAdd = false; 454 } 455 456 Imm = SImm; 457 return isAdd; 458} 459 460/// getBranchTargetOpValue - Helper function to get the branch target operand, 461/// which is either an immediate or requires a fixup. 462static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 463 unsigned FixupKind, 464 SmallVectorImpl<MCFixup> &Fixups) { 465 const MCOperand &MO = MI.getOperand(OpIdx); 466 467 // If the destination is an immediate, we have nothing to do. 468 if (MO.isImm()) return MO.getImm(); 469 assert(MO.isExpr() && "Unexpected branch target type!"); 470 const MCExpr *Expr = MO.getExpr(); 471 MCFixupKind Kind = MCFixupKind(FixupKind); 472 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 473 474 // All of the information is in the fixup. 475 return 0; 476} 477 478// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are 479// determined by negating them and XOR'ing them with bit 23. 480static int32_t encodeThumbBLOffset(int32_t offset) { 481 offset >>= 1; 482 uint32_t S = (offset & 0x800000) >> 23; 483 uint32_t J1 = (offset & 0x400000) >> 22; 484 uint32_t J2 = (offset & 0x200000) >> 21; 485 J1 = (~J1 & 0x1); 486 J2 = (~J2 & 0x1); 487 J1 ^= S; 488 J2 ^= S; 489 490 offset &= ~0x600000; 491 offset |= J1 << 22; 492 offset |= J2 << 21; 493 494 return offset; 495} 496 497/// getThumbBLTargetOpValue - Return encoding info for immediate branch target. 498uint32_t ARMMCCodeEmitter:: 499getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 500 SmallVectorImpl<MCFixup> &Fixups) const { 501 const MCOperand MO = MI.getOperand(OpIdx); 502 if (MO.isExpr()) 503 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, 504 Fixups); 505 return encodeThumbBLOffset(MO.getImm()); 506} 507 508/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate 509/// BLX branch target. 510uint32_t ARMMCCodeEmitter:: 511getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 512 SmallVectorImpl<MCFixup> &Fixups) const { 513 const MCOperand MO = MI.getOperand(OpIdx); 514 if (MO.isExpr()) 515 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, 516 Fixups); 517 return encodeThumbBLOffset(MO.getImm()); 518} 519 520/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. 521uint32_t ARMMCCodeEmitter:: 522getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 523 SmallVectorImpl<MCFixup> &Fixups) const { 524 const MCOperand MO = MI.getOperand(OpIdx); 525 if (MO.isExpr()) 526 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, 527 Fixups); 528 return (MO.getImm() >> 1); 529} 530 531/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. 532uint32_t ARMMCCodeEmitter:: 533getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 534 SmallVectorImpl<MCFixup> &Fixups) const { 535 const MCOperand MO = MI.getOperand(OpIdx); 536 if (MO.isExpr()) 537 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, 538 Fixups); 539 return (MO.getImm() >> 1); 540} 541 542/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. 543uint32_t ARMMCCodeEmitter:: 544getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 545 SmallVectorImpl<MCFixup> &Fixups) const { 546 const MCOperand MO = MI.getOperand(OpIdx); 547 if (MO.isExpr()) 548 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups); 549 return (MO.getImm() >> 1); 550} 551 552/// Return true if this branch has a non-always predication 553static bool HasConditionalBranch(const MCInst &MI) { 554 int NumOp = MI.getNumOperands(); 555 if (NumOp >= 2) { 556 for (int i = 0; i < NumOp-1; ++i) { 557 const MCOperand &MCOp1 = MI.getOperand(i); 558 const MCOperand &MCOp2 = MI.getOperand(i + 1); 559 if (MCOp1.isImm() && MCOp2.isReg() && 560 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { 561 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL) 562 return true; 563 } 564 } 565 } 566 return false; 567} 568 569/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 570/// target. 571uint32_t ARMMCCodeEmitter:: 572getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 573 SmallVectorImpl<MCFixup> &Fixups) const { 574 // FIXME: This really, really shouldn't use TargetMachine. We don't want 575 // coupling between MC and TM anywhere we can help it. 576 if (isThumb2()) 577 return 578 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups); 579 return getARMBranchTargetOpValue(MI, OpIdx, Fixups); 580} 581 582/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch 583/// target. 584uint32_t ARMMCCodeEmitter:: 585getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 586 SmallVectorImpl<MCFixup> &Fixups) const { 587 const MCOperand MO = MI.getOperand(OpIdx); 588 if (MO.isExpr()) { 589 if (HasConditionalBranch(MI)) 590 return ::getBranchTargetOpValue(MI, OpIdx, 591 ARM::fixup_arm_condbranch, Fixups); 592 return ::getBranchTargetOpValue(MI, OpIdx, 593 ARM::fixup_arm_uncondbranch, Fixups); 594 } 595 596 return MO.getImm() >> 2; 597} 598 599uint32_t ARMMCCodeEmitter:: 600getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 601 SmallVectorImpl<MCFixup> &Fixups) const { 602 const MCOperand MO = MI.getOperand(OpIdx); 603 if (MO.isExpr()) { 604 if (HasConditionalBranch(MI)) 605 return ::getBranchTargetOpValue(MI, OpIdx, 606 ARM::fixup_arm_condbl, Fixups); 607 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups); 608 } 609 610 return MO.getImm() >> 2; 611} 612 613uint32_t ARMMCCodeEmitter:: 614getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 615 SmallVectorImpl<MCFixup> &Fixups) const { 616 const MCOperand MO = MI.getOperand(OpIdx); 617 if (MO.isExpr()) 618 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups); 619 620 return MO.getImm() >> 1; 621} 622 623/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit 624/// immediate branch target. 625uint32_t ARMMCCodeEmitter:: 626getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 627 SmallVectorImpl<MCFixup> &Fixups) const { 628 unsigned Val = 629 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups); 630 bool I = (Val & 0x800000); 631 bool J1 = (Val & 0x400000); 632 bool J2 = (Val & 0x200000); 633 if (I ^ J1) 634 Val &= ~0x400000; 635 else 636 Val |= 0x400000; 637 638 if (I ^ J2) 639 Val &= ~0x200000; 640 else 641 Val |= 0x200000; 642 643 return Val; 644} 645 646/// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate 647/// ADR label target. 648uint32_t ARMMCCodeEmitter:: 649getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 650 SmallVectorImpl<MCFixup> &Fixups) const { 651 const MCOperand MO = MI.getOperand(OpIdx); 652 if (MO.isExpr()) 653 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, 654 Fixups); 655 int32_t offset = MO.getImm(); 656 uint32_t Val = 0x2000; 657 658 if (offset == INT32_MIN) { 659 Val = 0x1000; 660 offset = 0; 661 } else if (offset < 0) { 662 Val = 0x1000; 663 offset *= -1; 664 } 665 666 int SoImmVal = ARM_AM::getSOImmVal(offset); 667 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 668 669 Val |= SoImmVal; 670 return Val; 671} 672 673/// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label 674/// target. 675uint32_t ARMMCCodeEmitter:: 676getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 677 SmallVectorImpl<MCFixup> &Fixups) const { 678 const MCOperand MO = MI.getOperand(OpIdx); 679 if (MO.isExpr()) 680 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, 681 Fixups); 682 int32_t Val = MO.getImm(); 683 if (Val == INT32_MIN) 684 Val = 0x1000; 685 else if (Val < 0) { 686 Val *= -1; 687 Val |= 0x1000; 688 } 689 return Val; 690} 691 692/// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label 693/// target. 694uint32_t ARMMCCodeEmitter:: 695getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, 696 SmallVectorImpl<MCFixup> &Fixups) const { 697 const MCOperand MO = MI.getOperand(OpIdx); 698 if (MO.isExpr()) 699 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, 700 Fixups); 701 return MO.getImm(); 702} 703 704/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg' 705/// operand. 706uint32_t ARMMCCodeEmitter:: 707getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, 708 SmallVectorImpl<MCFixup> &) const { 709 // [Rn, Rm] 710 // {5-3} = Rm 711 // {2-0} = Rn 712 const MCOperand &MO1 = MI.getOperand(OpIdx); 713 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); 714 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); 715 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg()); 716 return (Rm << 3) | Rn; 717} 718 719/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. 720uint32_t ARMMCCodeEmitter:: 721getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, 722 SmallVectorImpl<MCFixup> &Fixups) const { 723 // {17-13} = reg 724 // {12} = (U)nsigned (add == '1', sub == '0') 725 // {11-0} = imm12 726 unsigned Reg, Imm12; 727 bool isAdd = true; 728 // If The first operand isn't a register, we have a label reference. 729 const MCOperand &MO = MI.getOperand(OpIdx); 730 if (!MO.isReg()) { 731 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 732 Imm12 = 0; 733 isAdd = false ; // 'U' bit is set as part of the fixup. 734 735 if (MO.isExpr()) { 736 const MCExpr *Expr = MO.getExpr(); 737 738 MCFixupKind Kind; 739 if (isThumb2()) 740 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); 741 else 742 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); 743 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 744 745 ++MCNumCPRelocations; 746 } else { 747 Reg = ARM::PC; 748 int32_t Offset = MO.getImm(); 749 // FIXME: Handle #-0. 750 if (Offset < 0) { 751 Offset *= -1; 752 isAdd = false; 753 } 754 Imm12 = Offset; 755 } 756 } else 757 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); 758 759 uint32_t Binary = Imm12 & 0xfff; 760 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 761 if (isAdd) 762 Binary |= (1 << 12); 763 Binary |= (Reg << 13); 764 return Binary; 765} 766 767/// getT2Imm8s4OpValue - Return encoding info for 768/// '+/- imm8<<2' operand. 769uint32_t ARMMCCodeEmitter:: 770getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, 771 SmallVectorImpl<MCFixup> &Fixups) const { 772 // FIXME: The immediate operand should have already been encoded like this 773 // before ever getting here. The encoder method should just need to combine 774 // the MI operands for the register and the offset into a single 775 // representation for the complex operand in the .td file. This isn't just 776 // style, unfortunately. As-is, we can't represent the distinct encoding 777 // for #-0. 778 779 // {8} = (U)nsigned (add == '1', sub == '0') 780 // {7-0} = imm8 781 int32_t Imm8 = MI.getOperand(OpIdx).getImm(); 782 bool isAdd = Imm8 >= 0; 783 784 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 785 if (Imm8 < 0) 786 Imm8 = -(uint32_t)Imm8; 787 788 // Scaled by 4. 789 Imm8 /= 4; 790 791 uint32_t Binary = Imm8 & 0xff; 792 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 793 if (isAdd) 794 Binary |= (1 << 8); 795 return Binary; 796} 797 798/// getT2AddrModeImm8s4OpValue - Return encoding info for 799/// 'reg +/- imm8<<2' operand. 800uint32_t ARMMCCodeEmitter:: 801getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, 802 SmallVectorImpl<MCFixup> &Fixups) const { 803 // {12-9} = reg 804 // {8} = (U)nsigned (add == '1', sub == '0') 805 // {7-0} = imm8 806 unsigned Reg, Imm8; 807 bool isAdd = true; 808 // If The first operand isn't a register, we have a label reference. 809 const MCOperand &MO = MI.getOperand(OpIdx); 810 if (!MO.isReg()) { 811 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 812 Imm8 = 0; 813 isAdd = false ; // 'U' bit is set as part of the fixup. 814 815 assert(MO.isExpr() && "Unexpected machine operand type!"); 816 const MCExpr *Expr = MO.getExpr(); 817 MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 818 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 819 820 ++MCNumCPRelocations; 821 } else 822 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); 823 824 // FIXME: The immediate operand should have already been encoded like this 825 // before ever getting here. The encoder method should just need to combine 826 // the MI operands for the register and the offset into a single 827 // representation for the complex operand in the .td file. This isn't just 828 // style, unfortunately. As-is, we can't represent the distinct encoding 829 // for #-0. 830 uint32_t Binary = (Imm8 >> 2) & 0xff; 831 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 832 if (isAdd) 833 Binary |= (1 << 8); 834 Binary |= (Reg << 9); 835 return Binary; 836} 837 838/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 839/// 'reg + imm8<<2' operand. 840uint32_t ARMMCCodeEmitter:: 841getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, 842 SmallVectorImpl<MCFixup> &Fixups) const { 843 // {11-8} = reg 844 // {7-0} = imm8 845 const MCOperand &MO = MI.getOperand(OpIdx); 846 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 847 unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 848 unsigned Imm8 = MO1.getImm(); 849 return (Reg << 8) | Imm8; 850} 851 852// FIXME: This routine assumes that a binary 853// expression will always result in a PCRel expression 854// In reality, its only true if one or more subexpressions 855// is itself a PCRel (i.e. "." in asm or some other pcrel construct) 856// but this is good enough for now. 857static bool EvaluateAsPCRel(const MCExpr *Expr) { 858 switch (Expr->getKind()) { 859 default: llvm_unreachable("Unexpected expression type"); 860 case MCExpr::SymbolRef: return false; 861 case MCExpr::Binary: return true; 862 } 863} 864 865uint32_t 866ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 867 SmallVectorImpl<MCFixup> &Fixups) const { 868 // {20-16} = imm{15-12} 869 // {11-0} = imm{11-0} 870 const MCOperand &MO = MI.getOperand(OpIdx); 871 if (MO.isImm()) 872 // Hi / lo 16 bits already extracted during earlier passes. 873 return static_cast<unsigned>(MO.getImm()); 874 875 // Handle :upper16: and :lower16: assembly prefixes. 876 const MCExpr *E = MO.getExpr(); 877 MCFixupKind Kind; 878 if (E->getKind() == MCExpr::Target) { 879 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E); 880 E = ARM16Expr->getSubExpr(); 881 882 switch (ARM16Expr->getKind()) { 883 default: llvm_unreachable("Unsupported ARMFixup"); 884 case ARMMCExpr::VK_ARM_HI16: 885 if (!isTargetDarwin() && EvaluateAsPCRel(E)) 886 Kind = MCFixupKind(isThumb2() 887 ? ARM::fixup_t2_movt_hi16_pcrel 888 : ARM::fixup_arm_movt_hi16_pcrel); 889 else 890 Kind = MCFixupKind(isThumb2() 891 ? ARM::fixup_t2_movt_hi16 892 : ARM::fixup_arm_movt_hi16); 893 break; 894 case ARMMCExpr::VK_ARM_LO16: 895 if (!isTargetDarwin() && EvaluateAsPCRel(E)) 896 Kind = MCFixupKind(isThumb2() 897 ? ARM::fixup_t2_movw_lo16_pcrel 898 : ARM::fixup_arm_movw_lo16_pcrel); 899 else 900 Kind = MCFixupKind(isThumb2() 901 ? ARM::fixup_t2_movw_lo16 902 : ARM::fixup_arm_movw_lo16); 903 break; 904 } 905 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc())); 906 return 0; 907 } 908 // If the expression doesn't have :upper16: or :lower16: on it, 909 // it's just a plain immediate expression, and those evaluate to 910 // the lower 16 bits of the expression regardless of whether 911 // we have a movt or a movw. 912 if (!isTargetDarwin() && EvaluateAsPCRel(E)) 913 Kind = MCFixupKind(isThumb2() 914 ? ARM::fixup_t2_movw_lo16_pcrel 915 : ARM::fixup_arm_movw_lo16_pcrel); 916 else 917 Kind = MCFixupKind(isThumb2() 918 ? ARM::fixup_t2_movw_lo16 919 : ARM::fixup_arm_movw_lo16); 920 Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc())); 921 return 0; 922} 923 924uint32_t ARMMCCodeEmitter:: 925getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, 926 SmallVectorImpl<MCFixup> &Fixups) const { 927 const MCOperand &MO = MI.getOperand(OpIdx); 928 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 929 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 930 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 931 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); 932 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); 933 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; 934 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); 935 unsigned SBits = getShiftOp(ShOp); 936 937 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift 938 // amount. However, it would be an easy mistake to make so check here. 939 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount"); 940 941 // {16-13} = Rn 942 // {12} = isAdd 943 // {11-0} = shifter 944 // {3-0} = Rm 945 // {4} = 0 946 // {6-5} = type 947 // {11-7} = imm 948 uint32_t Binary = Rm; 949 Binary |= Rn << 13; 950 Binary |= SBits << 5; 951 Binary |= ShImm << 7; 952 if (isAdd) 953 Binary |= 1 << 12; 954 return Binary; 955} 956 957uint32_t ARMMCCodeEmitter:: 958getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, 959 SmallVectorImpl<MCFixup> &Fixups) const { 960 // {17-14} Rn 961 // {13} 1 == imm12, 0 == Rm 962 // {12} isAdd 963 // {11-0} imm12/Rm 964 const MCOperand &MO = MI.getOperand(OpIdx); 965 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 966 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups); 967 Binary |= Rn << 14; 968 return Binary; 969} 970 971uint32_t ARMMCCodeEmitter:: 972getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, 973 SmallVectorImpl<MCFixup> &Fixups) const { 974 // {13} 1 == imm12, 0 == Rm 975 // {12} isAdd 976 // {11-0} imm12/Rm 977 const MCOperand &MO = MI.getOperand(OpIdx); 978 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 979 unsigned Imm = MO1.getImm(); 980 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; 981 bool isReg = MO.getReg() != 0; 982 uint32_t Binary = ARM_AM::getAM2Offset(Imm); 983 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12 984 if (isReg) { 985 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); 986 Binary <<= 7; // Shift amount is bits [11:7] 987 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] 988 Binary |= CTX.getRegisterInfo().getEncodingValue(MO.getReg()); // Rm is bits [3:0] 989 } 990 return Binary | (isAdd << 12) | (isReg << 13); 991} 992 993uint32_t ARMMCCodeEmitter:: 994getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, 995 SmallVectorImpl<MCFixup> &Fixups) const { 996 // {4} isAdd 997 // {3-0} Rm 998 const MCOperand &MO = MI.getOperand(OpIdx); 999 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1000 bool isAdd = MO1.getImm() != 0; 1001 return CTX.getRegisterInfo().getEncodingValue(MO.getReg()) | (isAdd << 4); 1002} 1003 1004uint32_t ARMMCCodeEmitter:: 1005getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, 1006 SmallVectorImpl<MCFixup> &Fixups) const { 1007 // {9} 1 == imm8, 0 == Rm 1008 // {8} isAdd 1009 // {7-4} imm7_4/zero 1010 // {3-0} imm3_0/Rm 1011 const MCOperand &MO = MI.getOperand(OpIdx); 1012 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1013 unsigned Imm = MO1.getImm(); 1014 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1015 bool isImm = MO.getReg() == 0; 1016 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1017 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1018 if (!isImm) 1019 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1020 return Imm8 | (isAdd << 8) | (isImm << 9); 1021} 1022 1023uint32_t ARMMCCodeEmitter:: 1024getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, 1025 SmallVectorImpl<MCFixup> &Fixups) const { 1026 // {13} 1 == imm8, 0 == Rm 1027 // {12-9} Rn 1028 // {8} isAdd 1029 // {7-4} imm7_4/zero 1030 // {3-0} imm3_0/Rm 1031 const MCOperand &MO = MI.getOperand(OpIdx); 1032 const MCOperand &MO1 = MI.getOperand(OpIdx+1); 1033 const MCOperand &MO2 = MI.getOperand(OpIdx+2); 1034 1035 // If The first operand isn't a register, we have a label reference. 1036 if (!MO.isReg()) { 1037 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 1038 1039 assert(MO.isExpr() && "Unexpected machine operand type!"); 1040 const MCExpr *Expr = MO.getExpr(); 1041 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled); 1042 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 1043 1044 ++MCNumCPRelocations; 1045 return (Rn << 9) | (1 << 13); 1046 } 1047 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1048 unsigned Imm = MO2.getImm(); 1049 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; 1050 bool isImm = MO1.getReg() == 0; 1051 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm); 1052 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8 1053 if (!isImm) 1054 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); 1055 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); 1056} 1057 1058/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. 1059uint32_t ARMMCCodeEmitter:: 1060getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, 1061 SmallVectorImpl<MCFixup> &Fixups) const { 1062 // [SP, #imm] 1063 // {7-0} = imm8 1064 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1065 assert(MI.getOperand(OpIdx).getReg() == ARM::SP && 1066 "Unexpected base register!"); 1067 1068 // The immediate is already shifted for the implicit zeroes, so no change 1069 // here. 1070 return MO1.getImm() & 0xff; 1071} 1072 1073/// getAddrModeISOpValue - Encode the t_addrmode_is# operands. 1074uint32_t ARMMCCodeEmitter:: 1075getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, 1076 SmallVectorImpl<MCFixup> &Fixups) const { 1077 // [Rn, #imm] 1078 // {7-3} = imm5 1079 // {2-0} = Rn 1080 const MCOperand &MO = MI.getOperand(OpIdx); 1081 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1082 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1083 unsigned Imm5 = MO1.getImm(); 1084 return ((Imm5 & 0x1f) << 3) | Rn; 1085} 1086 1087/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. 1088uint32_t ARMMCCodeEmitter:: 1089getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, 1090 SmallVectorImpl<MCFixup> &Fixups) const { 1091 const MCOperand MO = MI.getOperand(OpIdx); 1092 if (MO.isExpr()) 1093 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups); 1094 return (MO.getImm() >> 2); 1095} 1096 1097/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand. 1098uint32_t ARMMCCodeEmitter:: 1099getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, 1100 SmallVectorImpl<MCFixup> &Fixups) const { 1101 // {12-9} = reg 1102 // {8} = (U)nsigned (add == '1', sub == '0') 1103 // {7-0} = imm8 1104 unsigned Reg, Imm8; 1105 bool isAdd; 1106 // If The first operand isn't a register, we have a label reference. 1107 const MCOperand &MO = MI.getOperand(OpIdx); 1108 if (!MO.isReg()) { 1109 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 1110 Imm8 = 0; 1111 isAdd = false; // 'U' bit is handled as part of the fixup. 1112 1113 assert(MO.isExpr() && "Unexpected machine operand type!"); 1114 const MCExpr *Expr = MO.getExpr(); 1115 MCFixupKind Kind; 1116 if (isThumb2()) 1117 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); 1118 else 1119 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); 1120 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); 1121 1122 ++MCNumCPRelocations; 1123 } else { 1124 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); 1125 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; 1126 } 1127 1128 uint32_t Binary = ARM_AM::getAM5Offset(Imm8); 1129 // Immediate is always encoded as positive. The 'U' bit controls add vs sub. 1130 if (isAdd) 1131 Binary |= (1 << 8); 1132 Binary |= (Reg << 9); 1133 return Binary; 1134} 1135 1136unsigned ARMMCCodeEmitter:: 1137getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, 1138 SmallVectorImpl<MCFixup> &Fixups) const { 1139 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be 1140 // shifted. The second is Rs, the amount to shift by, and the third specifies 1141 // the type of the shift. 1142 // 1143 // {3-0} = Rm. 1144 // {4} = 1 1145 // {6-5} = type 1146 // {11-8} = Rs 1147 // {7} = 0 1148 1149 const MCOperand &MO = MI.getOperand(OpIdx); 1150 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1151 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); 1152 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1153 1154 // Encode Rm. 1155 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1156 1157 // Encode the shift opcode. 1158 unsigned SBits = 0; 1159 unsigned Rs = MO1.getReg(); 1160 if (Rs) { 1161 // Set shift operand (bit[7:4]). 1162 // LSL - 0001 1163 // LSR - 0011 1164 // ASR - 0101 1165 // ROR - 0111 1166 switch (SOpc) { 1167 default: llvm_unreachable("Unknown shift opc!"); 1168 case ARM_AM::lsl: SBits = 0x1; break; 1169 case ARM_AM::lsr: SBits = 0x3; break; 1170 case ARM_AM::asr: SBits = 0x5; break; 1171 case ARM_AM::ror: SBits = 0x7; break; 1172 } 1173 } 1174 1175 Binary |= SBits << 4; 1176 1177 // Encode the shift operation Rs. 1178 // Encode Rs bit[11:8]. 1179 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1180 return Binary | (CTX.getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift); 1181} 1182 1183unsigned ARMMCCodeEmitter:: 1184getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, 1185 SmallVectorImpl<MCFixup> &Fixups) const { 1186 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1187 // shifted. The second is the amount to shift by. 1188 // 1189 // {3-0} = Rm. 1190 // {4} = 0 1191 // {6-5} = type 1192 // {11-7} = imm 1193 1194 const MCOperand &MO = MI.getOperand(OpIdx); 1195 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1196 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1197 1198 // Encode Rm. 1199 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1200 1201 // Encode the shift opcode. 1202 unsigned SBits = 0; 1203 1204 // Set shift operand (bit[6:4]). 1205 // LSL - 000 1206 // LSR - 010 1207 // ASR - 100 1208 // ROR - 110 1209 // RRX - 110 and bit[11:8] clear. 1210 switch (SOpc) { 1211 default: llvm_unreachable("Unknown shift opc!"); 1212 case ARM_AM::lsl: SBits = 0x0; break; 1213 case ARM_AM::lsr: SBits = 0x2; break; 1214 case ARM_AM::asr: SBits = 0x4; break; 1215 case ARM_AM::ror: SBits = 0x6; break; 1216 case ARM_AM::rrx: 1217 Binary |= 0x60; 1218 return Binary; 1219 } 1220 1221 // Encode shift_imm bit[11:7]. 1222 Binary |= SBits << 4; 1223 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); 1224 assert(Offset < 32 && "Offset must be in range 0-31!"); 1225 return Binary | (Offset << 7); 1226} 1227 1228 1229unsigned ARMMCCodeEmitter:: 1230getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, 1231 SmallVectorImpl<MCFixup> &Fixups) const { 1232 const MCOperand &MO1 = MI.getOperand(OpNum); 1233 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1234 const MCOperand &MO3 = MI.getOperand(OpNum+2); 1235 1236 // Encoded as [Rn, Rm, imm]. 1237 // FIXME: Needs fixup support. 1238 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); 1239 Value <<= 4; 1240 Value |= CTX.getRegisterInfo().getEncodingValue(MO2.getReg()); 1241 Value <<= 2; 1242 Value |= MO3.getImm(); 1243 1244 return Value; 1245} 1246 1247unsigned ARMMCCodeEmitter:: 1248getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, 1249 SmallVectorImpl<MCFixup> &Fixups) const { 1250 const MCOperand &MO1 = MI.getOperand(OpNum); 1251 const MCOperand &MO2 = MI.getOperand(OpNum+1); 1252 1253 // FIXME: Needs fixup support. 1254 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); 1255 1256 // Even though the immediate is 8 bits long, we need 9 bits in order 1257 // to represent the (inverse of the) sign bit. 1258 Value <<= 9; 1259 int32_t tmp = (int32_t)MO2.getImm(); 1260 if (tmp < 0) 1261 tmp = abs(tmp); 1262 else 1263 Value |= 256; // Set the ADD bit 1264 Value |= tmp & 255; 1265 return Value; 1266} 1267 1268unsigned ARMMCCodeEmitter:: 1269getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, 1270 SmallVectorImpl<MCFixup> &Fixups) const { 1271 const MCOperand &MO1 = MI.getOperand(OpNum); 1272 1273 // FIXME: Needs fixup support. 1274 unsigned Value = 0; 1275 int32_t tmp = (int32_t)MO1.getImm(); 1276 if (tmp < 0) 1277 tmp = abs(tmp); 1278 else 1279 Value |= 256; // Set the ADD bit 1280 Value |= tmp & 255; 1281 return Value; 1282} 1283 1284unsigned ARMMCCodeEmitter:: 1285getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, 1286 SmallVectorImpl<MCFixup> &Fixups) const { 1287 const MCOperand &MO1 = MI.getOperand(OpNum); 1288 1289 // FIXME: Needs fixup support. 1290 unsigned Value = 0; 1291 int32_t tmp = (int32_t)MO1.getImm(); 1292 if (tmp < 0) 1293 tmp = abs(tmp); 1294 else 1295 Value |= 4096; // Set the ADD bit 1296 Value |= tmp & 4095; 1297 return Value; 1298} 1299 1300unsigned ARMMCCodeEmitter:: 1301getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, 1302 SmallVectorImpl<MCFixup> &Fixups) const { 1303 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be 1304 // shifted. The second is the amount to shift by. 1305 // 1306 // {3-0} = Rm. 1307 // {4} = 0 1308 // {6-5} = type 1309 // {11-7} = imm 1310 1311 const MCOperand &MO = MI.getOperand(OpIdx); 1312 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); 1313 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); 1314 1315 // Encode Rm. 1316 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1317 1318 // Encode the shift opcode. 1319 unsigned SBits = 0; 1320 // Set shift operand (bit[6:4]). 1321 // LSL - 000 1322 // LSR - 010 1323 // ASR - 100 1324 // ROR - 110 1325 switch (SOpc) { 1326 default: llvm_unreachable("Unknown shift opc!"); 1327 case ARM_AM::lsl: SBits = 0x0; break; 1328 case ARM_AM::lsr: SBits = 0x2; break; 1329 case ARM_AM::asr: SBits = 0x4; break; 1330 case ARM_AM::rrx: // FALLTHROUGH 1331 case ARM_AM::ror: SBits = 0x6; break; 1332 } 1333 1334 Binary |= SBits << 4; 1335 if (SOpc == ARM_AM::rrx) 1336 return Binary; 1337 1338 // Encode shift_imm bit[11:7]. 1339 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7; 1340} 1341 1342unsigned ARMMCCodeEmitter:: 1343getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, 1344 SmallVectorImpl<MCFixup> &Fixups) const { 1345 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the 1346 // msb of the mask. 1347 const MCOperand &MO = MI.getOperand(Op); 1348 uint32_t v = ~MO.getImm(); 1349 uint32_t lsb = CountTrailingZeros_32(v); 1350 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1; 1351 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!"); 1352 return lsb | (msb << 5); 1353} 1354 1355unsigned ARMMCCodeEmitter:: 1356getRegisterListOpValue(const MCInst &MI, unsigned Op, 1357 SmallVectorImpl<MCFixup> &Fixups) const { 1358 // VLDM/VSTM: 1359 // {12-8} = Vd 1360 // {7-0} = Number of registers 1361 // 1362 // LDM/STM: 1363 // {15-0} = Bitfield of GPRs. 1364 unsigned Reg = MI.getOperand(Op).getReg(); 1365 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg); 1366 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg); 1367 1368 unsigned Binary = 0; 1369 1370 if (SPRRegs || DPRRegs) { 1371 // VLDM/VSTM 1372 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg); 1373 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 1374 Binary |= (RegNo & 0x1f) << 8; 1375 if (SPRRegs) 1376 Binary |= NumRegs; 1377 else 1378 Binary |= NumRegs * 2; 1379 } else { 1380 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { 1381 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(MI.getOperand(I).getReg()); 1382 Binary |= 1 << RegNo; 1383 } 1384 } 1385 1386 return Binary; 1387} 1388 1389/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along 1390/// with the alignment operand. 1391unsigned ARMMCCodeEmitter:: 1392getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, 1393 SmallVectorImpl<MCFixup> &Fixups) const { 1394 const MCOperand &Reg = MI.getOperand(Op); 1395 const MCOperand &Imm = MI.getOperand(Op + 1); 1396 1397 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg()); 1398 unsigned Align = 0; 1399 1400 switch (Imm.getImm()) { 1401 default: break; 1402 case 2: 1403 case 4: 1404 case 8: Align = 0x01; break; 1405 case 16: Align = 0x02; break; 1406 case 32: Align = 0x03; break; 1407 } 1408 1409 return RegNo | (Align << 4); 1410} 1411 1412/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number 1413/// along with the alignment operand for use in VST1 and VLD1 with size 32. 1414unsigned ARMMCCodeEmitter:: 1415getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, 1416 SmallVectorImpl<MCFixup> &Fixups) const { 1417 const MCOperand &Reg = MI.getOperand(Op); 1418 const MCOperand &Imm = MI.getOperand(Op + 1); 1419 1420 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg()); 1421 unsigned Align = 0; 1422 1423 switch (Imm.getImm()) { 1424 default: break; 1425 case 8: 1426 case 16: 1427 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes. 1428 case 2: Align = 0x00; break; 1429 case 4: Align = 0x03; break; 1430 } 1431 1432 return RegNo | (Align << 4); 1433} 1434 1435 1436/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and 1437/// alignment operand for use in VLD-dup instructions. This is the same as 1438/// getAddrMode6AddressOpValue except for the alignment encoding, which is 1439/// different for VLD4-dup. 1440unsigned ARMMCCodeEmitter:: 1441getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, 1442 SmallVectorImpl<MCFixup> &Fixups) const { 1443 const MCOperand &Reg = MI.getOperand(Op); 1444 const MCOperand &Imm = MI.getOperand(Op + 1); 1445 1446 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg()); 1447 unsigned Align = 0; 1448 1449 switch (Imm.getImm()) { 1450 default: break; 1451 case 2: 1452 case 4: 1453 case 8: Align = 0x01; break; 1454 case 16: Align = 0x03; break; 1455 } 1456 1457 return RegNo | (Align << 4); 1458} 1459 1460unsigned ARMMCCodeEmitter:: 1461getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, 1462 SmallVectorImpl<MCFixup> &Fixups) const { 1463 const MCOperand &MO = MI.getOperand(Op); 1464 if (MO.getReg() == 0) return 0x0D; 1465 return CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 1466} 1467 1468unsigned ARMMCCodeEmitter:: 1469getShiftRight8Imm(const MCInst &MI, unsigned Op, 1470 SmallVectorImpl<MCFixup> &Fixups) const { 1471 return 8 - MI.getOperand(Op).getImm(); 1472} 1473 1474unsigned ARMMCCodeEmitter:: 1475getShiftRight16Imm(const MCInst &MI, unsigned Op, 1476 SmallVectorImpl<MCFixup> &Fixups) const { 1477 return 16 - MI.getOperand(Op).getImm(); 1478} 1479 1480unsigned ARMMCCodeEmitter:: 1481getShiftRight32Imm(const MCInst &MI, unsigned Op, 1482 SmallVectorImpl<MCFixup> &Fixups) const { 1483 return 32 - MI.getOperand(Op).getImm(); 1484} 1485 1486unsigned ARMMCCodeEmitter:: 1487getShiftRight64Imm(const MCInst &MI, unsigned Op, 1488 SmallVectorImpl<MCFixup> &Fixups) const { 1489 return 64 - MI.getOperand(Op).getImm(); 1490} 1491 1492void ARMMCCodeEmitter:: 1493EncodeInstruction(const MCInst &MI, raw_ostream &OS, 1494 SmallVectorImpl<MCFixup> &Fixups) const { 1495 // Pseudo instructions don't get encoded. 1496 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 1497 uint64_t TSFlags = Desc.TSFlags; 1498 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) 1499 return; 1500 1501 int Size; 1502 if (Desc.getSize() == 2 || Desc.getSize() == 4) 1503 Size = Desc.getSize(); 1504 else 1505 llvm_unreachable("Unexpected instruction size!"); 1506 1507 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); 1508 // Thumb 32-bit wide instructions need to emit the high order halfword 1509 // first. 1510 if (isThumb() && Size == 4) { 1511 EmitConstant(Binary >> 16, 2, OS); 1512 EmitConstant(Binary & 0xffff, 2, OS); 1513 } else 1514 EmitConstant(Binary, Size, OS); 1515 ++MCNumEmitted; // Keep track of the # of mi's emitted. 1516} 1517 1518#include "ARMGenMCCodeEmitter.inc" 1519