Searched refs:VT (Results 26 - 50 of 102) sorted by relevance

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/macosx-10.10/llvmCore-3425.0.34/lib/Target/NVPTX/
H A DNVPTXISelLowering.h79 bool isTypeSupportedInIntrinsic(MVT VT) const;
94 virtual EVT getSetCCResultType(EVT VT) const {
100 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/
H A DX86ISelLowering.h497 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
518 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
536 virtual EVT getSetCCResultType(EVT VT) const;
583 EVT VT) const;
632 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
639 EVT VT) const;
646 EVT VT) const;
651 virtual bool ShouldShrinkFPConstant(EVT VT) const {
655 return !X86ScalarSSEf64 || VT == MVT::f80;
664 bool isScalarFPTypeInSSEReg(EVT VT) cons
[all...]
/macosx-10.10/efax-38/efax/
H A Defaxmsg.h14 VT, FF, CR, SO, SI, DLE, XON, DC2, XOFF,DC4, NAK, enumerator in enum:cchar
/macosx-10.10/llvmCore-3425.0.34/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp255 EVT VT = N.getValueType();
258 AM.Base.Reg = CurDAG->getRegister(0, VT);
307 EVT VT = LD->getMemoryVT();
309 switch (VT.getSimpleVT().SimpleTy) {
334 MVT VT = LD->getMemoryVT().getSimpleVT();
337 switch (VT.SimpleTy) {
349 VT, MVT::i16, MVT::Other,
363 MVT VT = LD->getMemoryVT().getSimpleVT();
364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
370 VT, MV
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H A DMSP430ISelLowering.cpp222 EVT VT) const {
228 if (VT == MVT::i8)
235 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
594 EVT VT = Op.getValueType(); local
603 VT, N->getOperand(0), N->getOperand(1));
606 VT, N->getOperand(0), N->getOperand(1));
609 VT, N->getOperand(0), N->getOperand(1));
622 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
628 dl, VT, Victim);
817 EVT VT local
866 EVT VT = Op.getValueType(); local
922 EVT VT = Op.getValueType(); local
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/macosx-10.10/llvmCore-3425.0.34/include/llvm/CodeGen/
H A DSelectionDAGNodes.h349 static const EVT *getValueTypeList(EVT VT);
677 static SDVTList getSDVTList(EVT VT) {
678 SDVTList Ret = { getValueTypeList(VT), 1 };
894 // MemoryVT - VT of in-memory value.
1118 ShuffleVectorSDNode(EVT VT, DebugLoc dl, SDValue N1, SDValue N2, argument
1120 : SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {
1126 EVT VT = getValueType(0); local
1127 return makeArrayRef(Mask, VT.getVectorNumElements());
1137 EVT VT = getValueType(0);
1138 for (unsigned i = 0, e = VT
1155 ConstantSDNode(bool isTarget, const ConstantInt *val, EVT VT) argument
1180 ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT) argument
1251 FrameIndexSDNode(int fi, EVT VT, bool isTarg) argument
1270 JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned char TF) argument
1295 ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o, unsigned Align, unsigned char TF) argument
1303 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, EVT VT, int o, unsigned Align, unsigned char TF) argument
1355 TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned char TF) argument
1454 RegisterSDNode(unsigned reg, EVT VT) argument
1489 BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba, int64_t o, unsigned char Flags) argument
1528 ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, EVT VT) argument
1566 CvtRndSatSDNode(EVT VT, DebugLoc dl, const SDValue *Ops, unsigned NumOps, ISD::CvtCode Code) argument
1586 VTSDNode(EVT VT) argument
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/Hexagon/
H A DHexagonISelLowering.h128 virtual EVT getSetCCResultType(EVT VT) const {
139 EVT VT) const;
150 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
H A DHexagonInstrInfo.h108 unsigned createVR(MachineFunction* MF, MVT VT) const;
147 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/MBlaze/
H A DMBlazeISelLowering.h105 EVT getSetCCResultType(EVT VT) const;
168 EVT VT) const;
175 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
H A DMBlazeISelDAGToDAG.cpp211 EVT VT = Node->getValueType(0); local
212 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
/macosx-10.10/llvmCore-3425.0.34/lib/VMCore/
H A DValueTypes.cpp29 EVT VT; local
30 VT.LLVMTy = IntegerType::get(Context, BitWidth);
31 assert(VT.isExtended() && "Type is not extended!");
32 return VT;
35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, argument
38 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements);
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCISelLowering.cpp318 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; local
320 // add/sub are legal for all supported vector VT's.
321 setOperationAction(ISD::ADD , VT, Legal);
322 setOperationAction(ISD::SUB , VT, Legal);
325 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
326 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
329 setOperationAction(ISD::AND , VT, Promote);
330 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
331 setOperationAction(ISD::OR , VT, Promote);
332 AddPromotedToType (ISD::OR , VT, MV
1119 EVT VT; local
1338 EVT VT = Op.getOperand(0).getValueType(); local
1364 EVT VT = Op.getValueType(); local
1375 EVT VT = Node->getValueType(0); local
2517 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; local
2548 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; local
2569 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; local
2854 EVT VT = VA.getValVT(); local
3347 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); local
3981 EVT VT = Op.getValueType(); local
4023 EVT VT = Op.getValueType(); local
4052 EVT VT = Op.getValueType(); local
4082 EVT VT = Op.getValueType(); local
4115 BuildSplatI(int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, DebugLoc dl) argument
4163 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, DebugLoc dl) argument
4412 EVT VT = OpLHS.getValueType(); local
4429 EVT VT = Op.getValueType(); local
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/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp284 EVT VT = N->getValueType(0); local
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
291 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
564 EVT VT = N->getValueType(0); local
565 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
605 // Truncate to NVT instead of VT
703 EVT VT = N->getValueType(0); local
706 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
707 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
1180 MVT VT local
1766 EVT VT = N->getValueType(0); local
1776 EVT VT = N->getValueType(0); local
1792 EVT VT = N->getValueType(0); local
1910 EVT VT = N->getValueType(0); local
2042 EVT VT = N->getValueType(0); local
2062 EVT VT = N->getValueType(0); local
2097 EVT VT = LHSL.getValueType(); local
2209 EVT VT = N->getValueType(0); local
2263 EVT VT = N->getValueType(0); local
2349 EVT VT = N->getValueType(0); local
2369 EVT VT = N->getValueType(0); local
2418 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT(); local
2681 EVT VT = N->getOperand(1).getValueType(); local
2767 EVTToAPFloatSemantics(EVT VT) argument
2899 EVT VT = N->getValueType(0); local
[all...]
H A DLegalizeVectorTypes.cpp1395 EVT VT = WidenVT; local
1396 unsigned NumElts = VT.getVectorNumElements();
1397 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1399 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1402 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1414 EVT MaxVT = VT;
1430 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1432 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1434 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1440 VT
1655 EVT VT = N->getValueType(0); local
1739 EVT VT = N->getValueType(0); local
1902 EVT VT = N->getValueType(0); local
2032 EVT VT = N->getValueType(0); local
2140 EVT VT = N->getValueType(0); local
2161 EVT VT = N->getValueType(0); local
2187 EVT VT = N->getValueType(0); local
2290 unsigned VT; local
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H A DScheduleDAGRRList.cpp271 EVT VT = RegDefPos.GetValue(); local
275 if (VT == MVT::Untyped) {
295 RegClass = TLI->getRepRegClassFor(VT)->getID();
296 Cost = TLI->getRepRegClassCostFor(VT);
927 EVT VT = N->getValueType(i); local
928 if (VT == MVT::Glue)
930 else if (VT == MVT::Other)
935 EVT VT = Op.getNode()->getValueType(Op.getResNo()); local
936 if (VT == MVT::Glue)
1392 EVT VT local
[all...]
H A DLegalizeFloatTypes.cpp28 static RTLIB::Libcall GetFPLibCall(EVT VT, argument
34 VT == MVT::f32 ? Call_F32 :
35 VT == MVT::f64 ? Call_F64 :
36 VT == MVT::f80 ? Call_F80 :
37 VT == MVT::ppcf128 ? Call_PPCF128 :
474 EVT VT = N->getValueType(0); local
475 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
499 return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL));
525 EVT VT = N->getValueType(0); local
526 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
616 EVT VT = NewLHS.getValueType(); local
1168 EVT VT = N->getValueType(0); local
[all...]
H A DSelectionDAGPrinter.cpp93 EVT VT = Op.getValueType(); local
94 if (VT == MVT::Glue)
96 else if (VT == MVT::Other)
/macosx-10.10/llvmCore-3425.0.34/utils/TableGen/
H A DDAGISelMatcher.h772 MVT::SimpleValueType VT; member in class:llvm::EmitIntegerMatcher
775 : Matcher(EmitInteger), Val(val), VT(vt) {}
778 MVT::SimpleValueType getVT() const { return VT; }
788 cast<EmitIntegerMatcher>(M)->VT == VT;
790 virtual unsigned getHashImpl() const { return (Val << 4) | VT; }
797 MVT::SimpleValueType VT; member in class:llvm::EmitStringIntegerMatcher
800 : Matcher(EmitStringInteger), Val(val), VT(vt) {}
803 MVT::SimpleValueType getVT() const { return VT; }
813 cast<EmitStringIntegerMatcher>(M)->VT
823 MVT::SimpleValueType VT; member in class:llvm::EmitRegisterMatcher
[all...]
H A DIntrinsicEmitter.cpp247 static void EncodeFixedValueType(MVT::SimpleValueType VT, argument
249 if (EVT(VT).isInteger()) {
250 unsigned BitWidth = EVT(VT).getSizeInBits();
261 switch (VT) {
291 MVT::SimpleValueType VT = getValueType(R->getValueAsDef("VT")); local
294 switch (VT) {
328 if (EVT(VT).isVector()) {
329 EVT VVT = VT;
343 EncodeFixedValueType(VT, Si
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H A DFastISelEmitter.cpp160 OS << "VT == "
175 MVT::SimpleValueType VT,
218 //if (Op->getType(0) != VT)
245 if (Op->getType(0) != VT)
495 MVT::SimpleValueType VT = RetVT;
498 VT = InstPatNode->getChild(0)->getType(0);
507 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates))
552 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
556 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
601 MVT::SimpleValueType VT
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H A DCodeGenTarget.h139 bool isLegalValueType(MVT::SimpleValueType VT) const {
142 if (LegalVTs[i] == VT) return true;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Mips/
H A DMipsISelLowering.h147 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
167 EVT getSetCCResultType(EVT VT) const;
240 EVT VT) const;
261 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp269 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
270 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
271 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
274 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1449 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) { argument
1456 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1461 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) { argument
1467 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Op
1472 PairQRegs(EVT VT, SDValue V0, SDValue V1) argument
1483 QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1499 QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1514 QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1608 EVT VT = N->getValueType(0); local
1745 EVT VT = N->getOperand(Vec0Idx).getValueType(); local
1893 EVT VT = N->getOperand(Vec0Idx).getValueType(); local
2008 EVT VT = N->getValueType(0); local
2082 EVT VT = N->getValueType(0); local
2282 EVT VT = N->getValueType(0); local
2382 EVT VT = N->getValueType(0); local
2411 EVT VT = N->getValueType(0); local
2730 EVT VT = N->getValueType(0); local
2750 EVT VT = N->getValueType(0); local
2770 EVT VT = N->getValueType(0); local
3282 EVT VT = N->getValueType(0); local
3293 EVT VT = N->getValueType(0); local
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/macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/
H A DSPUISelLowering.h109 virtual EVT getSetCCResultType(EVT VT) const;
140 EVT VT) const;
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Sparc/
H A DSparcISelLowering.h66 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;

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