Lines Matching refs:VT
269 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
270 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
271 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
274 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1449 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1456 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1461 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1467 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1472 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1478 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1483 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1494 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1499 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1509 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1514 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1524 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1608 EVT VT = N->getValueType(0);
1609 bool is64BitVector = VT.is64BitVector();
1613 switch (VT.getSimpleVT().SimpleTy) {
1633 ResTy = VT;
1721 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1745 EVT VT = N->getOperand(Vec0Idx).getValueType();
1746 bool is64BitVector = VT.is64BitVector();
1750 switch (VT.getSimpleVT().SimpleTy) {
1793 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1841 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1893 EVT VT = N->getOperand(Vec0Idx).getValueType();
1894 bool is64BitVector = VT.is64BitVector();
1899 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1912 switch (VT.getSimpleVT().SimpleTy) {
1959 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1987 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2008 EVT VT = N->getValueType(0);
2013 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2026 switch (VT.getSimpleVT().SimpleTy) {
2071 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2082 EVT VT = N->getValueType(0);
2096 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2108 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2282 EVT VT = N->getValueType(0);
2293 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2352 switch (VT.getSimpleVT().SimpleTy) {
2366 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2382 EVT VT = N->getValueType(0);
2402 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2411 EVT VT = N->getValueType(0);
2412 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2414 return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2576 EVT VT = N->getValueType(0);
2577 if (VT != MVT::i32)
2602 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2730 EVT VT = N->getValueType(0);
2731 switch (VT.getSimpleVT().SimpleTy) {
2746 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2750 EVT VT = N->getValueType(0);
2751 switch (VT.getSimpleVT().SimpleTy) {
2766 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2770 EVT VT = N->getValueType(0);
2771 switch (VT.getSimpleVT().SimpleTy) {
2785 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
3282 EVT VT = N->getValueType(0);
3289 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3293 EVT VT = N->getValueType(0);
3305 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT,