1//===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend emits code for use by the "fast" instruction
11// selection algorithm. See the comments at the top of
12// lib/CodeGen/SelectionDAG/FastISel.cpp for background.
13//
14// This file scans through the target's tablegen instruction-info files
15// and extracts instructions with obvious-looking patterns, and it emits
16// code to look up these instructions by type and operator.
17//
18//===----------------------------------------------------------------------===//
19
20#include "CodeGenDAGPatterns.h"
21#include "llvm/ADT/SmallString.h"
22#include "llvm/Support/Debug.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/TableGen/Error.h"
25#include "llvm/TableGen/Record.h"
26#include "llvm/TableGen/TableGenBackend.h"
27using namespace llvm;
28
29
30/// InstructionMemo - This class holds additional information about an
31/// instruction needed to emit code for it.
32///
33namespace {
34struct InstructionMemo {
35  std::string Name;
36  const CodeGenRegisterClass *RC;
37  std::string SubRegNo;
38  std::vector<std::string>* PhysRegs;
39};
40} // End anonymous namespace
41
42/// ImmPredicateSet - This uniques predicates (represented as a string) and
43/// gives them unique (small) integer ID's that start at 0.
44namespace {
45class ImmPredicateSet {
46  DenseMap<TreePattern *, unsigned> ImmIDs;
47  std::vector<TreePredicateFn> PredsByName;
48public:
49
50  unsigned getIDFor(TreePredicateFn Pred) {
51    unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
52    if (Entry == 0) {
53      PredsByName.push_back(Pred);
54      Entry = PredsByName.size();
55    }
56    return Entry-1;
57  }
58
59  const TreePredicateFn &getPredicate(unsigned i) {
60    assert(i < PredsByName.size());
61    return PredsByName[i];
62  }
63
64  typedef std::vector<TreePredicateFn>::const_iterator iterator;
65  iterator begin() const { return PredsByName.begin(); }
66  iterator end() const { return PredsByName.end(); }
67
68};
69} // End anonymous namespace
70
71/// OperandsSignature - This class holds a description of a list of operand
72/// types. It has utility methods for emitting text based on the operands.
73///
74namespace {
75struct OperandsSignature {
76  class OpKind {
77    enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
78    char Repr;
79  public:
80
81    OpKind() : Repr(OK_Invalid) {}
82
83    bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
84    bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
85
86    static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
87    static OpKind getFP()  { OpKind K; K.Repr = OK_FP; return K; }
88    static OpKind getImm(unsigned V) {
89      assert((unsigned)OK_Imm+V < 128 &&
90             "Too many integer predicates for the 'Repr' char");
91      OpKind K; K.Repr = OK_Imm+V; return K;
92    }
93
94    bool isReg() const { return Repr == OK_Reg; }
95    bool isFP() const  { return Repr == OK_FP; }
96    bool isImm() const { return Repr >= OK_Imm; }
97
98    unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; }
99
100    void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
101                             bool StripImmCodes) const {
102      if (isReg())
103        OS << 'r';
104      else if (isFP())
105        OS << 'f';
106      else {
107        OS << 'i';
108        if (!StripImmCodes)
109          if (unsigned Code = getImmCode())
110            OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName();
111      }
112    }
113  };
114
115
116  SmallVector<OpKind, 3> Operands;
117
118  bool operator<(const OperandsSignature &O) const {
119    return Operands < O.Operands;
120  }
121  bool operator==(const OperandsSignature &O) const {
122    return Operands == O.Operands;
123  }
124
125  bool empty() const { return Operands.empty(); }
126
127  bool hasAnyImmediateCodes() const {
128    for (unsigned i = 0, e = Operands.size(); i != e; ++i)
129      if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
130        return true;
131    return false;
132  }
133
134  /// getWithoutImmCodes - Return a copy of this with any immediate codes forced
135  /// to zero.
136  OperandsSignature getWithoutImmCodes() const {
137    OperandsSignature Result;
138    for (unsigned i = 0, e = Operands.size(); i != e; ++i)
139      if (!Operands[i].isImm())
140        Result.Operands.push_back(Operands[i]);
141      else
142        Result.Operands.push_back(OpKind::getImm(0));
143    return Result;
144  }
145
146  void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
147    bool EmittedAnything = false;
148    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
149      if (!Operands[i].isImm()) continue;
150
151      unsigned Code = Operands[i].getImmCode();
152      if (Code == 0) continue;
153
154      if (EmittedAnything)
155        OS << " &&\n        ";
156
157      TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
158
159      // Emit the type check.
160      OS << "VT == "
161         << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0))
162         << " && ";
163
164
165      OS << PredFn.getFnName() << "(imm" << i <<')';
166      EmittedAnything = true;
167    }
168  }
169
170  /// initialize - Examine the given pattern and initialize the contents
171  /// of the Operands array accordingly. Return true if all the operands
172  /// are supported, false otherwise.
173  ///
174  bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
175                  MVT::SimpleValueType VT,
176                  ImmPredicateSet &ImmediatePredicates) {
177    if (InstPatNode->isLeaf())
178      return false;
179
180    if (InstPatNode->getOperator()->getName() == "imm") {
181      Operands.push_back(OpKind::getImm(0));
182      return true;
183    }
184
185    if (InstPatNode->getOperator()->getName() == "fpimm") {
186      Operands.push_back(OpKind::getFP());
187      return true;
188    }
189
190    const CodeGenRegisterClass *DstRC = 0;
191
192    for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
193      TreePatternNode *Op = InstPatNode->getChild(i);
194
195      // Handle imm operands specially.
196      if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
197        unsigned PredNo = 0;
198        if (!Op->getPredicateFns().empty()) {
199          TreePredicateFn PredFn = Op->getPredicateFns()[0];
200          // If there is more than one predicate weighing in on this operand
201          // then we don't handle it.  This doesn't typically happen for
202          // immediates anyway.
203          if (Op->getPredicateFns().size() > 1 ||
204              !PredFn.isImmediatePattern())
205            return false;
206          // Ignore any instruction with 'FastIselShouldIgnore', these are
207          // not needed and just bloat the fast instruction selector.  For
208          // example, X86 doesn't need to generate code to match ADD16ri8 since
209          // ADD16ri will do just fine.
210          Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
211          if (Rec->getValueAsBit("FastIselShouldIgnore"))
212            return false;
213
214          PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
215        }
216
217        // Handle unmatched immediate sizes here.
218        //if (Op->getType(0) != VT)
219        //  return false;
220
221        Operands.push_back(OpKind::getImm(PredNo));
222        continue;
223      }
224
225
226      // For now, filter out any operand with a predicate.
227      // For now, filter out any operand with multiple values.
228      if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
229        return false;
230
231      if (!Op->isLeaf()) {
232         if (Op->getOperator()->getName() == "fpimm") {
233          Operands.push_back(OpKind::getFP());
234          continue;
235        }
236        // For now, ignore other non-leaf nodes.
237        return false;
238      }
239
240      assert(Op->hasTypeSet(0) && "Type infererence not done?");
241
242      // For now, all the operands must have the same type (if they aren't
243      // immediates).  Note that this causes us to reject variable sized shifts
244      // on X86.
245      if (Op->getType(0) != VT)
246        return false;
247
248      DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
249      if (!OpDI)
250        return false;
251      Record *OpLeafRec = OpDI->getDef();
252
253      // For now, the only other thing we accept is register operands.
254      const CodeGenRegisterClass *RC = 0;
255      if (OpLeafRec->isSubClassOf("RegisterOperand"))
256        OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
257      if (OpLeafRec->isSubClassOf("RegisterClass"))
258        RC = &Target.getRegisterClass(OpLeafRec);
259      else if (OpLeafRec->isSubClassOf("Register"))
260        RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
261      else
262        return false;
263
264      // For now, this needs to be a register class of some sort.
265      if (!RC)
266        return false;
267
268      // For now, all the operands must have the same register class or be
269      // a strict subclass of the destination.
270      if (DstRC) {
271        if (DstRC != RC && !DstRC->hasSubClass(RC))
272          return false;
273      } else
274        DstRC = RC;
275      Operands.push_back(OpKind::getReg());
276    }
277    return true;
278  }
279
280  void PrintParameters(raw_ostream &OS) const {
281    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
282      if (Operands[i].isReg()) {
283        OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
284      } else if (Operands[i].isImm()) {
285        OS << "uint64_t imm" << i;
286      } else if (Operands[i].isFP()) {
287        OS << "const ConstantFP *f" << i;
288      } else {
289        llvm_unreachable("Unknown operand kind!");
290      }
291      if (i + 1 != e)
292        OS << ", ";
293    }
294  }
295
296  void PrintArguments(raw_ostream &OS,
297                      const std::vector<std::string> &PR) const {
298    assert(PR.size() == Operands.size());
299    bool PrintedArg = false;
300    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
301      if (PR[i] != "")
302        // Implicit physical register operand.
303        continue;
304
305      if (PrintedArg)
306        OS << ", ";
307      if (Operands[i].isReg()) {
308        OS << "Op" << i << ", Op" << i << "IsKill";
309        PrintedArg = true;
310      } else if (Operands[i].isImm()) {
311        OS << "imm" << i;
312        PrintedArg = true;
313      } else if (Operands[i].isFP()) {
314        OS << "f" << i;
315        PrintedArg = true;
316      } else {
317        llvm_unreachable("Unknown operand kind!");
318      }
319    }
320  }
321
322  void PrintArguments(raw_ostream &OS) const {
323    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
324      if (Operands[i].isReg()) {
325        OS << "Op" << i << ", Op" << i << "IsKill";
326      } else if (Operands[i].isImm()) {
327        OS << "imm" << i;
328      } else if (Operands[i].isFP()) {
329        OS << "f" << i;
330      } else {
331        llvm_unreachable("Unknown operand kind!");
332      }
333      if (i + 1 != e)
334        OS << ", ";
335    }
336  }
337
338
339  void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
340                           ImmPredicateSet &ImmPredicates,
341                           bool StripImmCodes = false) const {
342    for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
343      if (PR[i] != "")
344        // Implicit physical register operand. e.g. Instruction::Mul expect to
345        // select to a binary op. On x86, mul may take a single operand with
346        // the other operand being implicit. We must emit something that looks
347        // like a binary instruction except for the very inner FastEmitInst_*
348        // call.
349        continue;
350      Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
351    }
352  }
353
354  void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
355                           bool StripImmCodes = false) const {
356    for (unsigned i = 0, e = Operands.size(); i != e; ++i)
357      Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
358  }
359};
360} // End anonymous namespace
361
362namespace {
363class FastISelMap {
364  typedef std::map<std::string, InstructionMemo> PredMap;
365  typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
366  typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
367  typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
368  typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
369            OperandsOpcodeTypeRetPredMap;
370
371  OperandsOpcodeTypeRetPredMap SimplePatterns;
372
373  std::map<OperandsSignature, std::vector<OperandsSignature> >
374    SignaturesWithConstantForms;
375
376  std::string InstNS;
377  ImmPredicateSet ImmediatePredicates;
378public:
379  explicit FastISelMap(std::string InstNS);
380
381  void collectPatterns(CodeGenDAGPatterns &CGP);
382  void printImmediatePredicates(raw_ostream &OS);
383  void printFunctionDefinitions(raw_ostream &OS);
384};
385} // End anonymous namespace
386
387static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
388  return CGP.getSDNodeInfo(Op).getEnumName();
389}
390
391static std::string getLegalCName(std::string OpName) {
392  std::string::size_type pos = OpName.find("::");
393  if (pos != std::string::npos)
394    OpName.replace(pos, 2, "_");
395  return OpName;
396}
397
398FastISelMap::FastISelMap(std::string instns)
399  : InstNS(instns) {
400}
401
402static std::string PhyRegForNode(TreePatternNode *Op,
403                                 const CodeGenTarget &Target) {
404  std::string PhysReg;
405
406  if (!Op->isLeaf())
407    return PhysReg;
408
409  DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
410  Record *OpLeafRec = OpDI->getDef();
411  if (!OpLeafRec->isSubClassOf("Register"))
412    return PhysReg;
413
414  PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
415             "Namespace")->getValue())->getValue();
416  PhysReg += "::";
417  PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
418  return PhysReg;
419}
420
421void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
422  const CodeGenTarget &Target = CGP.getTargetInfo();
423
424  // Determine the target's namespace name.
425  InstNS = Target.getInstNamespace() + "::";
426  assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
427
428  // Scan through all the patterns and record the simple ones.
429  for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
430       E = CGP.ptm_end(); I != E; ++I) {
431    const PatternToMatch &Pattern = *I;
432
433    // For now, just look at Instructions, so that we don't have to worry
434    // about emitting multiple instructions for a pattern.
435    TreePatternNode *Dst = Pattern.getDstPattern();
436    if (Dst->isLeaf()) continue;
437    Record *Op = Dst->getOperator();
438    if (!Op->isSubClassOf("Instruction"))
439      continue;
440    CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
441    if (II.Operands.empty())
442      continue;
443
444    // For now, ignore multi-instruction patterns.
445    bool MultiInsts = false;
446    for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
447      TreePatternNode *ChildOp = Dst->getChild(i);
448      if (ChildOp->isLeaf())
449        continue;
450      if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
451        MultiInsts = true;
452        break;
453      }
454    }
455    if (MultiInsts)
456      continue;
457
458    // For now, ignore instructions where the first operand is not an
459    // output register.
460    const CodeGenRegisterClass *DstRC = 0;
461    std::string SubRegNo;
462    if (Op->getName() != "EXTRACT_SUBREG") {
463      Record *Op0Rec = II.Operands[0].Rec;
464      if (Op0Rec->isSubClassOf("RegisterOperand"))
465        Op0Rec = Op0Rec->getValueAsDef("RegClass");
466      if (!Op0Rec->isSubClassOf("RegisterClass"))
467        continue;
468      DstRC = &Target.getRegisterClass(Op0Rec);
469      if (!DstRC)
470        continue;
471    } else {
472      // If this isn't a leaf, then continue since the register classes are
473      // a bit too complicated for now.
474      if (!Dst->getChild(1)->isLeaf()) continue;
475
476      DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue());
477      if (SR)
478        SubRegNo = getQualifiedName(SR->getDef());
479      else
480        SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
481    }
482
483    // Inspect the pattern.
484    TreePatternNode *InstPatNode = Pattern.getSrcPattern();
485    if (!InstPatNode) continue;
486    if (InstPatNode->isLeaf()) continue;
487
488    // Ignore multiple result nodes for now.
489    if (InstPatNode->getNumTypes() > 1) continue;
490
491    Record *InstPatOp = InstPatNode->getOperator();
492    std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
493    MVT::SimpleValueType RetVT = MVT::isVoid;
494    if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
495    MVT::SimpleValueType VT = RetVT;
496    if (InstPatNode->getNumChildren()) {
497      assert(InstPatNode->getChild(0)->getNumTypes() == 1);
498      VT = InstPatNode->getChild(0)->getType(0);
499    }
500
501    // For now, filter out any instructions with predicates.
502    if (!InstPatNode->getPredicateFns().empty())
503      continue;
504
505    // Check all the operands.
506    OperandsSignature Operands;
507    if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates))
508      continue;
509
510    std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
511    if (InstPatNode->getOperator()->getName() == "imm" ||
512        InstPatNode->getOperator()->getName() == "fpimm")
513      PhysRegInputs->push_back("");
514    else {
515      // Compute the PhysRegs used by the given pattern, and check that
516      // the mapping from the src to dst patterns is simple.
517      bool FoundNonSimplePattern = false;
518      unsigned DstIndex = 0;
519      for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
520        std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
521        if (PhysReg.empty()) {
522          if (DstIndex >= Dst->getNumChildren() ||
523              Dst->getChild(DstIndex)->getName() !=
524              InstPatNode->getChild(i)->getName()) {
525            FoundNonSimplePattern = true;
526            break;
527          }
528          ++DstIndex;
529        }
530
531        PhysRegInputs->push_back(PhysReg);
532      }
533
534      if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren())
535        FoundNonSimplePattern = true;
536
537      if (FoundNonSimplePattern)
538        continue;
539    }
540
541    // Get the predicate that guards this pattern.
542    std::string PredicateCheck = Pattern.getPredicateCheck();
543
544    // Ok, we found a pattern that we can handle. Remember it.
545    InstructionMemo Memo = {
546      Pattern.getDstPattern()->getOperator()->getName(),
547      DstRC,
548      SubRegNo,
549      PhysRegInputs
550    };
551
552    if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
553      throw TGError(Pattern.getSrcRecord()->getLoc(),
554                    "Duplicate record in FastISel table!");
555
556    SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
557
558    // If any of the operands were immediates with predicates on them, strip
559    // them down to a signature that doesn't have predicates so that we can
560    // associate them with the stripped predicate version.
561    if (Operands.hasAnyImmediateCodes()) {
562      SignaturesWithConstantForms[Operands.getWithoutImmCodes()]
563        .push_back(Operands);
564    }
565  }
566}
567
568void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
569  if (ImmediatePredicates.begin() == ImmediatePredicates.end())
570    return;
571
572  OS << "\n// FastEmit Immediate Predicate functions.\n";
573  for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
574       E = ImmediatePredicates.end(); I != E; ++I) {
575    OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
576    OS << I->getImmediatePredicateCode() << "\n}\n";
577  }
578
579  OS << "\n\n";
580}
581
582
583void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
584  // Now emit code for all the patterns that we collected.
585  for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
586       OE = SimplePatterns.end(); OI != OE; ++OI) {
587    const OperandsSignature &Operands = OI->first;
588    const OpcodeTypeRetPredMap &OTM = OI->second;
589
590    for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
591         I != E; ++I) {
592      const std::string &Opcode = I->first;
593      const TypeRetPredMap &TM = I->second;
594
595      OS << "// FastEmit functions for " << Opcode << ".\n";
596      OS << "\n";
597
598      // Emit one function for each opcode,type pair.
599      for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
600           TI != TE; ++TI) {
601        MVT::SimpleValueType VT = TI->first;
602        const RetPredMap &RM = TI->second;
603        if (RM.size() != 1) {
604          for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
605               RI != RE; ++RI) {
606            MVT::SimpleValueType RetVT = RI->first;
607            const PredMap &PM = RI->second;
608            bool HasPred = false;
609
610            OS << "unsigned FastEmit_"
611               << getLegalCName(Opcode)
612               << "_" << getLegalCName(getName(VT))
613               << "_" << getLegalCName(getName(RetVT)) << "_";
614            Operands.PrintManglingSuffix(OS, ImmediatePredicates);
615            OS << "(";
616            Operands.PrintParameters(OS);
617            OS << ") {\n";
618
619            // Emit code for each possible instruction. There may be
620            // multiple if there are subtarget concerns.
621            for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
622                 PI != PE; ++PI) {
623              std::string PredicateCheck = PI->first;
624              const InstructionMemo &Memo = PI->second;
625
626              if (PredicateCheck.empty()) {
627                assert(!HasPred &&
628                       "Multiple instructions match, at least one has "
629                       "a predicate and at least one doesn't!");
630              } else {
631                OS << "  if (" + PredicateCheck + ") {\n";
632                OS << "  ";
633                HasPred = true;
634              }
635
636              for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
637                if ((*Memo.PhysRegs)[i] != "")
638                  OS << "  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
639                     << "TII.get(TargetOpcode::COPY), "
640                     << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
641              }
642
643              OS << "  return FastEmitInst_";
644              if (Memo.SubRegNo.empty()) {
645                Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
646                                             ImmediatePredicates, true);
647                OS << "(" << InstNS << Memo.Name << ", ";
648                OS << "&" << InstNS << Memo.RC->getName() << "RegClass";
649                if (!Operands.empty())
650                  OS << ", ";
651                Operands.PrintArguments(OS, *Memo.PhysRegs);
652                OS << ");\n";
653              } else {
654                OS << "extractsubreg(" << getName(RetVT);
655                OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
656              }
657
658              if (HasPred)
659                OS << "  }\n";
660
661            }
662            // Return 0 if none of the predicates were satisfied.
663            if (HasPred)
664              OS << "  return 0;\n";
665            OS << "}\n";
666            OS << "\n";
667          }
668
669          // Emit one function for the type that demultiplexes on return type.
670          OS << "unsigned FastEmit_"
671             << getLegalCName(Opcode) << "_"
672             << getLegalCName(getName(VT)) << "_";
673          Operands.PrintManglingSuffix(OS, ImmediatePredicates);
674          OS << "(MVT RetVT";
675          if (!Operands.empty())
676            OS << ", ";
677          Operands.PrintParameters(OS);
678          OS << ") {\nswitch (RetVT.SimpleTy) {\n";
679          for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
680               RI != RE; ++RI) {
681            MVT::SimpleValueType RetVT = RI->first;
682            OS << "  case " << getName(RetVT) << ": return FastEmit_"
683               << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
684               << "_" << getLegalCName(getName(RetVT)) << "_";
685            Operands.PrintManglingSuffix(OS, ImmediatePredicates);
686            OS << "(";
687            Operands.PrintArguments(OS);
688            OS << ");\n";
689          }
690          OS << "  default: return 0;\n}\n}\n\n";
691
692        } else {
693          // Non-variadic return type.
694          OS << "unsigned FastEmit_"
695             << getLegalCName(Opcode) << "_"
696             << getLegalCName(getName(VT)) << "_";
697          Operands.PrintManglingSuffix(OS, ImmediatePredicates);
698          OS << "(MVT RetVT";
699          if (!Operands.empty())
700            OS << ", ";
701          Operands.PrintParameters(OS);
702          OS << ") {\n";
703
704          OS << "  if (RetVT.SimpleTy != " << getName(RM.begin()->first)
705             << ")\n    return 0;\n";
706
707          const PredMap &PM = RM.begin()->second;
708          bool HasPred = false;
709
710          // Emit code for each possible instruction. There may be
711          // multiple if there are subtarget concerns.
712          for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
713               ++PI) {
714            std::string PredicateCheck = PI->first;
715            const InstructionMemo &Memo = PI->second;
716
717            if (PredicateCheck.empty()) {
718              assert(!HasPred &&
719                     "Multiple instructions match, at least one has "
720                     "a predicate and at least one doesn't!");
721            } else {
722              OS << "  if (" + PredicateCheck + ") {\n";
723              OS << "  ";
724              HasPred = true;
725            }
726
727            for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
728              if ((*Memo.PhysRegs)[i] != "")
729                OS << "  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
730                   << "TII.get(TargetOpcode::COPY), "
731                   << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
732            }
733
734            OS << "  return FastEmitInst_";
735
736            if (Memo.SubRegNo.empty()) {
737              Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
738                                           ImmediatePredicates, true);
739              OS << "(" << InstNS << Memo.Name << ", ";
740              OS << "&" << InstNS << Memo.RC->getName() << "RegClass";
741              if (!Operands.empty())
742                OS << ", ";
743              Operands.PrintArguments(OS, *Memo.PhysRegs);
744              OS << ");\n";
745            } else {
746              OS << "extractsubreg(RetVT, Op0, Op0IsKill, ";
747              OS << Memo.SubRegNo;
748              OS << ");\n";
749            }
750
751             if (HasPred)
752               OS << "  }\n";
753          }
754
755          // Return 0 if none of the predicates were satisfied.
756          if (HasPred)
757            OS << "  return 0;\n";
758          OS << "}\n";
759          OS << "\n";
760        }
761      }
762
763      // Emit one function for the opcode that demultiplexes based on the type.
764      OS << "unsigned FastEmit_"
765         << getLegalCName(Opcode) << "_";
766      Operands.PrintManglingSuffix(OS, ImmediatePredicates);
767      OS << "(MVT VT, MVT RetVT";
768      if (!Operands.empty())
769        OS << ", ";
770      Operands.PrintParameters(OS);
771      OS << ") {\n";
772      OS << "  switch (VT.SimpleTy) {\n";
773      for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
774           TI != TE; ++TI) {
775        MVT::SimpleValueType VT = TI->first;
776        std::string TypeName = getName(VT);
777        OS << "  case " << TypeName << ": return FastEmit_"
778           << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
779        Operands.PrintManglingSuffix(OS, ImmediatePredicates);
780        OS << "(RetVT";
781        if (!Operands.empty())
782          OS << ", ";
783        Operands.PrintArguments(OS);
784        OS << ");\n";
785      }
786      OS << "  default: return 0;\n";
787      OS << "  }\n";
788      OS << "}\n";
789      OS << "\n";
790    }
791
792    OS << "// Top-level FastEmit function.\n";
793    OS << "\n";
794
795    // Emit one function for the operand signature that demultiplexes based
796    // on opcode and type.
797    OS << "unsigned FastEmit_";
798    Operands.PrintManglingSuffix(OS, ImmediatePredicates);
799    OS << "(MVT VT, MVT RetVT, unsigned Opcode";
800    if (!Operands.empty())
801      OS << ", ";
802    Operands.PrintParameters(OS);
803    OS << ") {\n";
804
805    // If there are any forms of this signature available that operand on
806    // constrained forms of the immediate (e.g. 32-bit sext immediate in a
807    // 64-bit operand), check them first.
808
809    std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
810      = SignaturesWithConstantForms.find(Operands);
811    if (MI != SignaturesWithConstantForms.end()) {
812      // Unique any duplicates out of the list.
813      std::sort(MI->second.begin(), MI->second.end());
814      MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
815                       MI->second.end());
816
817      // Check each in order it was seen.  It would be nice to have a good
818      // relative ordering between them, but we're not going for optimality
819      // here.
820      for (unsigned i = 0, e = MI->second.size(); i != e; ++i) {
821        OS << "  if (";
822        MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates);
823        OS << ")\n    if (unsigned Reg = FastEmit_";
824        MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates);
825        OS << "(VT, RetVT, Opcode";
826        if (!MI->second[i].empty())
827          OS << ", ";
828        MI->second[i].PrintArguments(OS);
829        OS << "))\n      return Reg;\n\n";
830      }
831
832      // Done with this, remove it.
833      SignaturesWithConstantForms.erase(MI);
834    }
835
836    OS << "  switch (Opcode) {\n";
837    for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
838         I != E; ++I) {
839      const std::string &Opcode = I->first;
840
841      OS << "  case " << Opcode << ": return FastEmit_"
842         << getLegalCName(Opcode) << "_";
843      Operands.PrintManglingSuffix(OS, ImmediatePredicates);
844      OS << "(VT, RetVT";
845      if (!Operands.empty())
846        OS << ", ";
847      Operands.PrintArguments(OS);
848      OS << ");\n";
849    }
850    OS << "  default: return 0;\n";
851    OS << "  }\n";
852    OS << "}\n";
853    OS << "\n";
854  }
855
856  // TODO: SignaturesWithConstantForms should be empty here.
857}
858
859namespace llvm {
860
861void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
862  CodeGenDAGPatterns CGP(RK);
863  const CodeGenTarget &Target = CGP.getTargetInfo();
864  emitSourceFileHeader("\"Fast\" Instruction Selector for the " +
865                       Target.getName() + " target", OS);
866
867  // Determine the target's namespace name.
868  std::string InstNS = Target.getInstNamespace() + "::";
869  assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
870
871  FastISelMap F(InstNS);
872  F.collectPatterns(CGP);
873  F.printImmediatePredicates(OS);
874  F.printFunctionDefinitions(OS);
875}
876
877} // End llvm namespace
878