Searched refs:xe (Results 226 - 250 of 934) sorted by relevance

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/linux-master/drivers/firewire/
H A Dohci.h154 #define OHCI1394_evt_unknown 0xe
157 #define OHCI1394_phy_tcode 0xe
/linux-master/drivers/gpu/drm/amd/include/asic_reg/athub/
H A Dathub_2_0_0_sh_mask.h97 #define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe
184 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
361 #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
743 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe
789 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe
822 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe
1072 #define XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
1083 #define XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
1094 #define XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
1105 #define XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
[all...]
/linux-master/drivers/staging/fbtft/
H A Dfb_hx8340bn.c109 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) argument
111 write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS, 0x00, xs, 0x00, xe);
H A Dfb_seps525.c150 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) argument
155 write_reg(par, SEPS525_MX2_ADDR, xe);
/linux-master/drivers/gpu/drm/amd/include/asic_reg/df/
H A Ddf_3_6_sh_mask.h80 #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk14__SHIFT 0xe
146 #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk14__SHIFT 0xe
H A Ddf_4_3_sh_mask.h40 #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk14__SHIFT 0xe
106 #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk14__SHIFT 0xe
/linux-master/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c234 [0xe] = "NVDEC1"
291 [0xe] = "RESERVED",
310 [0xe] = "RESERVED",
635 { 0x2, 0x1d, 0xe, 0x0, 0x30000000, 14, 0x30000000 },
704 { 0x3, 0x1d, 0xe, 0x2, 0x30000000, 14, 0x30000000 },
776 { 0x5, 0x1d, 0xe, 0x0, 0x30000000, 14, 0x30000000 },
1282 { 0x0, 0x5, 0xe, 0, 0x0b8b0000, 14, 0x00050000 },
1310 { 0x0, 0xb, 0xe, 0, 0x0b9a0000, 14, 0x00050000 },
1324 { 0x0, 0xe, 0x0, 0, 0x0b0f0000, 0, 0x00000000 },
1325 { 0x0, 0xe,
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_7_0_0_sh_mask.h122 #define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe
150 #define HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe
215 #define HDP_XDP_BUSY_STS__BUSY_BITS_14__SHIFT 0xe
262 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe
301 #define HDP_XDP_MMHUB_ERROR_CLR__HDP_RUSER_NACK_10_CLR__SHIFT 0xe
345 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
580 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe
596 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
/linux-master/drivers/gpu/drm/xe/
H A Dxe_gt_idle.c158 struct xe_device *xe = gt_to_xe(gt); local
184 return drmm_add_action_or_reset(&xe->drm, gt_idle_sysfs_fini, kobj);
H A Dxe_uc.c101 struct xe_device *xe = uc_to_xe(uc); local
106 drm_err(&xe->drm, "Failed to reset GuC, ret = %d\n", ret);
H A Dxe_gt_sriov_pf_config.c74 struct xe_device *xe = tile_to_xe(tile); local
79 bo = xe_bo_create_pin_map(xe, tile, NULL,
88 xe_map_memcpy_to(xe, &bo->vmap, 0, klvs, bytes);
303 struct xe_device *xe = gt_to_xe(gt); local
305 return IS_DGFX(xe) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K;
1245 struct xe_device *xe = gt_to_xe(gt); local
1250 for_each_tile(tile, xe, tid) {
1266 static void pf_force_lmtt_invalidate(struct xe_device *xe) argument
1271 static void pf_reset_vf_lmtt(struct xe_device *xe, unsigne argument
1283 pf_update_vf_lmtt(struct xe_device *xe, unsigned int vfid) argument
1352 struct xe_device *xe = gt_to_xe(gt); local
[all...]
H A Dxe_preempt_fence.c36 return "xe";
52 queue_work(q->vm->xe->preempt_fence_wq, &pfence->preempt_work);
H A Dxe_pt.c54 struct xe_device *xe = tile_to_xe(tile); local
55 u16 pat_index = xe->pat.idx[XE_CACHE_WB];
65 return vm->pt_ops->pte_encode_addr(xe, 0, pat_index, level, IS_DGFX(xe), 0) |
110 bo = xe_bo_create_pin_map(vm->xe, tile, vm, SZ_4K,
157 xe_map_memset(vm->xe, map, 0, 0, SZ_4K);
161 xe_pt_write(vm->xe, map, i, empty);
375 xe_pt_write(xe_walk->vm->xe, map, offset, pte);
600 struct xe_device *xe = tile_to_xe(tile); local
623 (is_devmem || !IS_DGFX(xe)))
895 xe_vm_dbg_print_entries(struct xe_device *xe, const struct xe_vm_pgtable_update *entries, unsigned int num_entries) argument
[all...]
/linux-master/arch/m68k/include/asm/
H A Dmcfwdebug.h24 #define MCFDEBUG_DBR 0xe /* Data breakpoint */
/linux-master/drivers/scsi/bnx2i/
H A D57xx_iscsi_constants.h74 #define ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_STATSN (0xe)
/linux-master/drivers/hid/
H A Dhid-roccat-koneplus.h55 KONEPLUS_COMMAND_E = 0xe,
/linux-master/include/sound/
H A Des1688.h50 #define e_s_s_ESS1688DATA_AVAIL 0xe
/linux-master/arch/microblaze/kernel/cpu/
H A Dcpuinfo.c72 {"virtex6", 0xe},
/linux-master/drivers/gpu/drm/amd/include/asic_reg/thm/
H A Dthm_11_0_2_sh_mask.h83 #define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe
/linux-master/drivers/media/platform/mediatek/jpeg/
H A Dmtk_jpeg_enc_hw.h44 #define JPEG_ENC_QUALITY_Q64 0xe
/linux-master/include/linux/mfd/
H A Dipaq-micro.h32 #define MSG_CODEC_CTRL 0xe /* H3100 only */
/linux-master/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf.h23 #define MAXIM_NEW2_RF 0xe
/linux-master/drivers/net/wireless/intel/iwlwifi/
H A Diwl-context-info.h53 IWL_CTXT_INFO_RB_SIZE_32K = 0xe,
/linux-master/drivers/vfio/pci/hisilicon/
H A Dhisi_acc_vfio_pci.h13 #define QM_MB_CMD_PAUSE_QM 0xe
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_0_0_sh_mask.h25 #define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_10_BIT__SHIFT 0xe
74 #define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe
83 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe
118 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe
205 #define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0xe
324 #define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe
359 #define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe
399 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe
572 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe
622 #define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_10_BIT__SHIFT 0xe
[all...]

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