/linux-master/scripts/dtc/include-prefixes/arm/nxp/imx/ |
H A D | imx7ulp-pinfunc.h | 16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 28 #define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 34 #define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 39 #define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 47 #define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 55 #define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 63 #define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 69 #define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 77 #define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa [all...] |
/linux-master/drivers/media/usb/dvb-usb/ |
H A D | af9005-script.h | 19 {0xa180, 0x0, 0x8, 0xa}, 26 {0xa20e, 0x4, 0x4, 0xa}, 29 {0xa32a, 0x0, 0x4, 0xa}, 44 {0xa01f, 0x0, 0x6, 0xa}, 45 {0xa020, 0x0, 0x6, 0xa}, 79 {0xa2bd, 0x0, 0x8, 0xa}, 108 {0xa60d, 0x0, 0x8, 0xa}, 169 {0xa105, 0x0, 0x7, 0xa}, 199 {0xa343, 0x0, 0x4, 0xa},
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_4_1_sh_mask.h | 56 #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa 116 #define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 168 #define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa 246 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa 282 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa 306 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa 338 #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa 420 #define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa 444 #define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa 544 #define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/df/ |
H A D | df_3_6_sh_mask.h | 59 #define DF_CS_UMC_AON0_DramLimitAddress0__AllowReqIO__SHIFT 0xa 76 #define DF_CS_UMC_AON0_HardwareAssertMaskLow__HWAssertMsk10__SHIFT 0xa 142 #define DF_NCS_PG0_HardwareAssertMaskHigh__HWAssertMsk10__SHIFT 0xa
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/dpcs/ |
H A D | dpcs_4_2_3_sh_mask.h | 142 #define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa 314 #define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa 428 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xa 476 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa 511 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa 641 #define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa 661 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa 781 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa 920 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa 966 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa [all...] |
H A D | dpcs_3_1_4_sh_mask.h | 41 #define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xa 61 #define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa 79 #define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT 0xa 304 #define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT 0xa 336 #define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT 0xa 391 #define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT 0xa 478 #define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT 0xa 554 #define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT 0xa 572 #define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT 0xa 590 #define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT 0xa [all...] |
H A D | dpcs_4_2_0_sh_mask.h | 138 #define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa 308 #define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa 420 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xa 468 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa 503 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa 618 #define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa 638 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa 758 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa 897 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa 943 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa [all...] |
H A D | dpcs_4_2_2_sh_mask.h | 125 #define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa 297 #define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT 0xa 411 #define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xa 459 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT 0xa 494 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa 624 #define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa 644 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa 764 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa 903 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa 949 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa [all...] |
/linux-master/io_uring/ |
H A D | tctx.c | 51 WARN_ON_ONCE(!xa_empty(&tctx->xa)); 84 xa_init(&tctx->xa); 115 if (!xa_load(&tctx->xa, (unsigned long)ctx)) { 122 ret = xa_err(xa_store(&tctx->xa, (unsigned long)ctx, 162 node = xa_erase(&tctx->xa, index); 184 xa_for_each(&tctx->xa, index, node) {
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/linux-master/drivers/net/ethernet/fungible/funeth/ |
H A D | fun_port.h | 17 PORT_MAC_RX_ifInUcastPkts = 0xa, 64 PORT_MAC_TX_etherStatsPkts65to127Octets = 0xa,
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
H A D | power_budget.c | 77 cap_entry = nvbios_rd08(bios, header + 0xa); 117 entry->max_w = nvbios_rd32(bios, entry_offset + 0xa);
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/linux-master/lib/ |
H A D | idr.c | 383 XA_STATE(xas, &ida->xa, min / IDA_BITMAP_BITS); 489 XA_STATE(xas, &ida->xa, id / IDA_BITMAP_BITS); 543 XA_STATE(xas, &ida->xa, 0); 594 struct xarray *xa = &ida->xa; local 595 pr_debug("ida: %p node %p free %d\n", ida, xa->xa_head, 596 xa->xa_flags >> ROOT_TAG_SHIFT); 597 ida_dump_entry(xa->xa_head, 0);
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/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_reg_whitelist.c | 148 if (!sr->name || xa_empty(&sr->xa)) 152 xa_for_each(&sr->xa, reg, entry)
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/linux-master/drivers/gpu/drm/panthor/ |
H A D | panthor_heap.c | 92 /** @lock: Lock protecting access to @xa. */ 95 /** @xa: Array storing panthor_heap objects. */ 96 struct xarray xa; member in struct:panthor_heap_pool 225 heap = xa_erase(&pool->xa, handle); 326 ret = xa_alloc(&pool->xa, &id, heap, 378 heap = xa_load(&pool->xa, heap_id); 441 heap = xa_load(&pool->xa, heap_id); 490 xa_destroy(&pool->xa); 547 xa_init_flags(&pool->xa, XA_FLAGS_ALLOC); 594 xa_for_each(&pool->xa, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gca/ |
H A D | gfx_8_1_sh_mask.h | 582 #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 594 #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 606 #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 618 #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 630 #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 642 #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 654 #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 666 #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 688 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 706 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa [all...] |
H A D | gfx_8_0_sh_mask.h | 580 #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 592 #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 604 #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 616 #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 628 #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 640 #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 652 #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 664 #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa 686 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 704 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa [all...] |
/linux-master/kernel/irq/ |
H A D | msi.c | 88 struct xarray *xa = &md->__domains[domid].store; local 99 ret = xa_alloc(xa, &index, desc, limit, GFP_KERNEL); 112 ret = xa_insert(xa, index, desc, GFP_KERNEL); 183 struct xarray *xa; local 191 xa = &dev->msi.data->__domains[ctrl->domid].store; 192 xa_for_each_range(xa, idx, desc, ctrl->first, ctrl->last) { 193 xa_erase(xa, idx); 353 struct xarray *xa = &md->__domains[domid].store; local 356 xa_for_each_start(xa, md->__iter_idx, desc, md->__iter_idx) { 436 struct xarray *xa; local 1111 struct xarray *xa; local 1160 struct xarray *xa; local 1280 struct xarray *xa = &dev->msi.data->__domains[ctrl->domid].store; local 1594 struct xarray *xa = &dev->msi.data->__domains[ctrl->domid].store; local [all...] |
/linux-master/arch/powerpc/platforms/cell/ |
H A D | interrupt.h | 54 IIC_UNIT_SPU_7 = 0xa,
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/linux-master/include/uapi/linux/ |
H A D | firewire-constants.h | 38 #define TCODE_STREAM_DATA 0xa
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/linux-master/drivers/hid/ |
H A D | hid-roccat-isku.h | 49 ISKU_COMMAND_KEYS_MEDIA = 0xa,
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/linux-master/drivers/iio/pressure/ |
H A D | zpa2326.h | 16 #define ZPA2326_REF_P_H_REG (0xa)
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/linux-master/include/linux/mfd/ |
H A D | as3711.h | 27 #define AS3711_LDO_7_VOLTAGE 0xa
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/linux-master/sound/soc/codecs/ |
H A D | wm8510.h | 20 #define WM8510_DAC 0xa
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H A D | wm8974.h | 20 #define WM8974_DAC 0xa
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/linux-master/drivers/staging/olpc_dcon/ |
H A D | olpc_dcon.h | 34 #define DCON_REG_BRIGHT 0xa
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