Searched refs:x3 (Results 226 - 250 of 4324) sorted by relevance

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/linux-master/sound/soc/codecs/
H A Drt5665.h511 #define RT5665_EXT_JD_SRC_JD1_2 (0x3 << 4)
517 #define RT5665_SEL_SHT_MID_TON_MASK (0x3 << 12)
580 #define RT5665_STO1_ADC_L_BST_MASK (0x3 << 14)
582 #define RT5665_STO1_ADC_R_BST_MASK (0x3 << 12)
586 #define RT5665_MONO_ADC_L_BST_MASK (0x3 << 14)
588 #define RT5665_MONO_ADC_R_BST_MASK (0x3 << 12)
592 #define RT5665_STO2_ADC_L_BST_MASK (0x3 << 14)
594 #define RT5665_STO2_ADC_R_BST_MASK (0x3 << 12)
608 #define RT5665_STO1_ADCL_SRC_MASK (0x3 << 10)
624 #define RT5665_STO1_ADCR_SRC_MASK (0x3 <<
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H A Drt1015.h184 #define RT1015_CLK_SYS_PRE_SEL_MASK (0x3 << 14)
223 #define RT1015_MONO_LR_SEL_MASK (0x3 << 4)
251 #define RT1015_I2S_DL_8 (0x3 << 8)
257 #define RT1015_I2S_M_DF_PCM_B (0x3)
267 #define RT1015_I2S_TCON_DF_PCM_B (0x3 << 13)
270 #define RT1015_TCON_BCLK_SEL_MASK (0x3 << 10)
275 #define RT1015_TCON_BCLK_SEL_256FS (0x3 << 10)
276 #define RT1015_TCON_CH_LEN_MASK (0x3 << 5)
281 #define RT1015_TCON_CH_LEN_32B (0x3 << 5)
290 #define RT1015_I2S_CH_TX_MASK (0x3 << 1
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H A Dda7213.h161 #define DA7213_SR_12000 (0x3 << 0)
179 #define DA7213_PLL_INDIV_36_TO_54_MHZ (0x3 << 2)
180 #define DA7213_PLL_INDIV_MASK (0x3 << 2)
191 #define DA7213_DAI_BCLKS_PER_WCLK_256 (0x3 << 0)
192 #define DA7213_DAI_BCLKS_PER_WCLK_MASK (0x3 << 0)
203 #define DA7213_DAI_FORMAT_DSP (0x3 << 0)
204 #define DA7213_DAI_FORMAT_MASK (0x3 << 0)
208 #define DA7213_DAI_WORD_LENGTH_S32_LE (0x3 << 2)
209 #define DA7213_DAI_WORD_LENGTH_MASK (0x3 << 2)
395 #define DA7213_MICBIAS1_LEVEL_MASK (0x3 <<
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H A Dmt6358.h249 #define RG_DIVCKS_PWD_NCP_ST_SEL_MASK 0x3
250 #define RG_DIVCKS_PWD_NCP_ST_SEL_MASK_SFT (0x3 << 0)
287 #define AUDIO_DIG_DSN_CBS_MASK 0x3
288 #define AUDIO_DIG_DSN_CBS_MASK_SFT (0x3 << 0)
290 #define AUDIO_DIG_DSN_BIX_MASK 0x3
291 #define AUDIO_DIG_DSN_BIX_MASK_SFT (0x3 << 2)
330 #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
331 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
381 #define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3
382 #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 1
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/linux-master/sound/soc/mediatek/mt6797/
H A Dmt6797-reg.h360 #define DAI_MODE_MASK 0x3
361 #define DAI_MODE_MASK_SFT (0x3 << 24)
410 #define MOD_DAI_MODE_MASK 0x3
411 #define MOD_DAI_MODE_MASK_SFT (0x3 << 30)
469 #define DL_2_OUTPUT_SEL_CTL_MASK 0x3
470 #define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24)
472 #define DL_2_FADEIN_0START_EN_MASK 0x3
473 #define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16)
490 #define DL2_ARAMPSP_CTL_PRE_MASK 0x3
491 #define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 <<
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/linux-master/drivers/usb/dwc2/
H A Dhw.h107 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_50 0x3
177 #define GRXSTS_DPID_MASK (0x3 << 15)
205 #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
232 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
234 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
243 #define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
249 #define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
256 #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
303 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
334 #define GLPMCFG_COREL1RES_MASK (0x3 << 1
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dvid.h480 #define RB_MAP_PKR0_MASK (0x3 << 0)
482 #define RB_MAP_PKR1_MASK (0x3 << 2)
484 #define RB_XSEL2_MASK (0x3 << 4)
488 #define PKR_MAP_MASK (0x3 << 8)
490 #define PKR_XSEL_MASK (0x3 << 10)
492 #define PKR_YSEL_MASK (0x3 << 12)
494 #define SC_MAP_MASK (0x3 << 16)
496 #define SC_XSEL_MASK (0x3 << 18)
498 #define SC_YSEL_MASK (0x3 << 20)
500 #define SE_MAP_MASK (0x3 << 2
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/linux-master/drivers/pmdomain/amlogic/
H A Dmeson-gx-pwrc-vpu.c59 0x3 << i, 0x3 << i);
64 0x3 << i, 0x3 << i);
97 0x3 << i, 0x3 << i);
102 0x3 << i, 0x3 << i);
107 0x3 << i, 0x3 <<
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/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_top.c93 status->mdp = (value >> 0) & 0x3;
94 status->sspp[SSPP_VIG0] = (value >> 4) & 0x3;
95 status->sspp[SSPP_VIG1] = (value >> 6) & 0x3;
96 status->sspp[SSPP_VIG2] = (value >> 8) & 0x3;
97 status->sspp[SSPP_VIG3] = (value >> 10) & 0x3;
98 status->sspp[SSPP_RGB0] = (value >> 12) & 0x3;
99 status->sspp[SSPP_RGB1] = (value >> 14) & 0x3;
100 status->sspp[SSPP_RGB2] = (value >> 16) & 0x3;
101 status->sspp[SSPP_RGB3] = (value >> 18) & 0x3;
102 status->sspp[SSPP_DMA0] = (value >> 20) & 0x3;
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/linux-master/drivers/pinctrl/
H A Dpinctrl-keembay.c44 #define KEEMBAY_GPIO_MODE_INV_VAL 0x3
143 KEEMBAY_MUX(0x3, "I2C0_M3"),
152 KEEMBAY_MUX(0x3, "I2C0_M3"),
161 KEEMBAY_MUX(0x3, "I2C1_M3"),
170 KEEMBAY_MUX(0x3, "I2C1_M3"),
179 KEEMBAY_MUX(0x3, "I2C2_M3"),
188 KEEMBAY_MUX(0x3, "I2C2_M3"),
197 KEEMBAY_MUX(0x3, "I2C3_M3"),
206 KEEMBAY_MUX(0x3, "I2C3_M3"),
215 KEEMBAY_MUX(0x3, "UART0_M
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/linux-master/drivers/crypto/
H A Datmel-aes-regs.h17 #define AES_MR_SMOD_MASK (0x3 << 8)
21 #define AES_MR_KEYSIZE_MASK (0x3 << 10)
29 #define AES_MR_OPMOD_CFB (0x3 << 12)
38 #define AES_MR_CFBS_16b (0x3 << 16)
56 #define AES_ISR_URAT_ODR_RD_SUBK (0x3 << 12)
/linux-master/drivers/gpu/drm/ingenic/
H A Dingenic-ipu.h71 #define JZ_IPU_D_FMT_IN_FMT_RGB565 (0x3 << JZ_IPU_D_FMT_IN_FMT_LSB)
77 #define JZ_IPU_D_FMT_YUV_VY1UY0 (0x3 << JZ_IPU_D_FMT_YUV_FMT_LSB)
78 #define JZ_IPU_D_FMT_IN_FMT_YUV411 (0x3 << JZ_IPU_D_FMT_IN_FMT_LSB)
84 #define JZ_IPU_D_FMT_OUT_FMT_YUV422 (0x3 << JZ_IPU_D_FMT_OUT_FMT_LSB)
91 #define JZ_IPU_D_FMT_RGB_OUT_OFT_GRB (0x3 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
/linux-master/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7620.c14 #define MT7620_GPIO_MODE_I2S_UARTF 0x3
23 #define MT7620_GPIO_MODE_ND_SD_MASK 0x3
29 #define MT7620_GPIO_MODE_PCIE_MASK 0x3
35 #define MT7620_GPIO_MODE_WDT_MASK 0x3
41 #define MT7620_GPIO_MODE_MDIO_MASK 0x3
H A Dpinctrl-rt3883.c14 #define RT3883_GPIO_MODE_I2S_UARTF 0x3
32 #define RT3883_GPIO_MODE_LNA_A_MASK 0x3
34 #define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
37 #define RT3883_GPIO_MODE_LNA_G_MASK 0x3
39 #define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
/linux-master/arch/arm/boot/dts/nxp/imx/
H A Dimx51-pinfunc.h18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
23 #define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
29 #define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
37 #define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
47 #define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
62 #define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
67 #define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
71 #define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
72 #define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
78 #define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3
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/linux-master/scripts/dtc/include-prefixes/arm/nxp/imx/
H A Dimx51-pinfunc.h18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
23 #define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
29 #define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
37 #define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
47 #define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
62 #define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
67 #define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
71 #define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
72 #define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
78 #define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_enum.h31 DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3,
51 DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3,
59 DCIO_UNIPHYD_FBDIV_CLK = 0x3,
67 DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3,
75 DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3,
83 DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3,
101 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3,
119 DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3,
125 DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3,
131 DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3,
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/linux-master/drivers/gpu/drm/exynos/
H A Dregs-decon7.h21 #define VIDOUTCON0_DUAL_MASK (0x3 << 24)
22 #define VIDOUTCON0_DUAL_ON (0x3 << 24)
56 #define WINCONx_BUFSTATUS (0x3 << 30)
57 #define WINCONx_BUFSEL_MASK (0x3 << 28)
76 #define WINCONx_BPPMODE_32BPP_BGRA (0x3 << 2)
202 #define BLENDE_COEF_ONE_MINUS_ALPHA_A 0x3
228 #define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
232 #define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
259 #define VIDCON1_VCLK_MASK (0x3 << 9)
262 #define VIDCON1_VCLK_RUN_VDEN_DISABLE (0x3 <<
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/linux-master/crypto/
H A Dseed.c333 u32 i, t0, t1, x1, x2, x3, x4; local
337 x3 = be32_to_cpu(key[2]);
341 t0 = x1 + x3 - KC[i];
353 t0 = x3;
354 x3 = (x3 << 8) ^ (x4 >> 24);
369 u32 x1, x2, x3, x4, t0, t1; local
374 x3 = be32_to_cpu(src[2]);
377 OP(x1, x2, x3, x4, 0);
378 OP(x3, x
407 u32 x1, x2, x3, x4, t0, t1; local
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/linux-master/drivers/net/wan/framer/pef2256/
H A Dpef2256-regs.h34 #define PEF2256_FMR0_XC_HDB3 FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x3)
39 #define PEF2256_FMR0_RC_HDB3 FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x3)
57 #define PEF2256_FMR2_RFS_AUTO_MULTIFRAME FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x3)
105 #define PEF2256_12_LIM1_RIL_420 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x3)
114 #define PEF2256_2X_LIM1_RIL_350 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x3)
132 #define PEF2256_LIM2_SLT_THR45 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x3)
152 #define PEF2256_SIC1_RBS_BYPASS FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x3)
157 #define PEF2256_SIC1_XBS_96BITS FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x3)
176 #define PEF2256_CMR1_RS_DCOR_8192 FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x3)
198 #define PEF2256_GPC1_CSFP_FSC_OUT_LOW FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x3)
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/linux-master/drivers/gpu/drm/radeon/
H A Dcik_reg.h36 # define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0)
40 # define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
45 # define CIK_GRPH_Z(x) (((x) & 0x3) << 4)
46 # define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
70 # define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
83 # define CIK_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
115 # define CIK_CURSOR_MODE(x) (((x) & 0x3) << 8)
/linux-master/sound/ppc/
H A Dawacs.h41 #define MASK_SSFSEL (0x3 << 15) /* Status SubFrame Select */
46 #define MASK_EMODESEL (0x3 << 22) /* Send info out on which frame? */
93 #define MASK_ADDR1RES1 (0x3) /* Reserved */
105 #define MASK_PAROUT (0x3 << 10) /* Parallel Out (???) */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
178 #define RATE_19200 (0x3 << 8) /* 19.2 kHz */
179 #define RATE_17640 (0x3 << 8) /* 17.64 kHz */
/linux-master/drivers/edac/
H A Dppc4xx_edac.h101 #define SDRAM_MCOPT1_MCHK_MASK PPC_REG_VAL(3, 0x3) /* ECC mask */
105 #define SDRAM_MCOPT1_MCHK_CHK_REP PPC_REG_VAL(3, 0x3) /* ECC gen/chk/rpt */
106 #define SDRAM_MCOPT1_MCHK_DECODE(n) ((((u32)(n)) >> 28) & 0x3)
125 #define SDRAM_MBCF_SZ_32MB PPC_REG_VAL(19, 0x3)
138 #define SDRAM_MBCF_AM_MODE3 PPC_REG_VAL(23, 0x3)
155 #define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3)
163 #define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3)
/linux-master/sound/soc/mediatek/mt8192/
H A Dmt8192-reg.h582 #define PCM_WLEN_MASK 0x3
583 #define PCM_WLEN_MASK_SFT (0x3 << 14)
600 #define PCM_MODE_MASK 0x3
601 #define PCM_MODE_MASK_SFT (0x3 << 3)
603 #define PCM_FMT_MASK 0x3
604 #define PCM_FMT_MASK_SFT (0x3 << 1)
635 #define DAI_PCM_LOOPBACK_CH_MASK 0x3
636 #define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 14)
638 #define I2S_PCM_LOOPBACK_CH_MASK 0x3
639 #define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 1
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/linux-master/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_msg_arm64.h40 #define X86_IO_W7_SIZE_MASK (0x3 << X86_IO_W7_SIZE_SHIFT)
58 register u64 x3 asm("x3") = flags | VMWARE_HYPERVISOR_PORT;
69 "+r"(x3), "+r"(x4), "+r"(x5)
75 *edx = x3;
91 register u64 x3 asm("x3") = flags | VMWARE_HYPERVISOR_PORT_HB;
102 "+r"(x3), "+r"(x4), "+r"(x5)
108 *edx = x3;

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