1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2008 Nuovation System Designs, LLC
4 *   Grant Erickson <gerickson@nuovations.com>
5 *
6 * This file defines processor mnemonics for accessing and managing
7 * the IBM DDR1/DDR2 ECC controller found in the 405EX[r], 440SP,
8 * 440SPe, 460EX, 460GT and 460SX.
9 */
10
11#ifndef __PPC4XX_EDAC_H
12#define __PPC4XX_EDAC_H
13
14#include <linux/types.h>
15
16/*
17 * Macro for generating register field mnemonics
18 */
19#define PPC_REG_BITS			32
20#define PPC_REG_VAL(bit, val)		((val) << ((PPC_REG_BITS - 1) - (bit)))
21#define PPC_REG_DECODE(bit, val)	((val) >> ((PPC_REG_BITS - 1) - (bit)))
22
23/*
24 * IBM 4xx DDR1/DDR2 SDRAM memory controller registers (at least those
25 * relevant to ECC)
26 */
27#define SDRAM_BESR			0x00	/* Error status (read/clear) */
28#define SDRAM_BESRT			0x01	/* Error statuss (test/set)  */
29#define SDRAM_BEARL			0x02	/* Error address low	     */
30#define SDRAM_BEARH			0x03	/* Error address high	     */
31#define SDRAM_WMIRQ			0x06	/* Write master (read/clear) */
32#define SDRAM_WMIRQT			0x07	/* Write master (test/set)   */
33#define SDRAM_MCOPT1			0x20	/* Controller options 1	     */
34#define SDRAM_MBXCF_BASE		0x40	/* Bank n configuration base */
35#define	SDRAM_MBXCF(n)			(SDRAM_MBXCF_BASE + (4 * (n)))
36#define SDRAM_MB0CF			SDRAM_MBXCF(0)
37#define SDRAM_MB1CF			SDRAM_MBXCF(1)
38#define SDRAM_MB2CF			SDRAM_MBXCF(2)
39#define SDRAM_MB3CF			SDRAM_MBXCF(3)
40#define SDRAM_ECCCR			0x98	/* ECC error status	     */
41#define SDRAM_ECCES			SDRAM_ECCCR
42
43/*
44 * PLB Master IDs
45 */
46#define	SDRAM_PLB_M0ID_FIRST		0
47#define	SDRAM_PLB_M0ID_ICU		SDRAM_PLB_M0ID_FIRST
48#define	SDRAM_PLB_M0ID_PCIE0		1
49#define	SDRAM_PLB_M0ID_PCIE1		2
50#define	SDRAM_PLB_M0ID_DMA		3
51#define	SDRAM_PLB_M0ID_DCU		4
52#define	SDRAM_PLB_M0ID_OPB		5
53#define	SDRAM_PLB_M0ID_MAL		6
54#define	SDRAM_PLB_M0ID_SEC		7
55#define	SDRAM_PLB_M0ID_AHB		8
56#define SDRAM_PLB_M0ID_LAST		SDRAM_PLB_M0ID_AHB
57#define SDRAM_PLB_M0ID_COUNT		(SDRAM_PLB_M0ID_LAST - \
58					 SDRAM_PLB_M0ID_FIRST + 1)
59
60/*
61 * Memory Controller Bus Error Status Register
62 */
63#define SDRAM_BESR_MASK			PPC_REG_VAL(7, 0xFF)
64#define SDRAM_BESR_M0ID_MASK		PPC_REG_VAL(3, 0xF)
65#define	SDRAM_BESR_M0ID_DECODE(n)	PPC_REG_DECODE(3, n)
66#define SDRAM_BESR_M0ID_ICU		PPC_REG_VAL(3, SDRAM_PLB_M0ID_ICU)
67#define SDRAM_BESR_M0ID_PCIE0		PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE0)
68#define SDRAM_BESR_M0ID_PCIE1		PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE1)
69#define SDRAM_BESR_M0ID_DMA		PPC_REG_VAL(3, SDRAM_PLB_M0ID_DMA)
70#define SDRAM_BESR_M0ID_DCU		PPC_REG_VAL(3, SDRAM_PLB_M0ID_DCU)
71#define SDRAM_BESR_M0ID_OPB		PPC_REG_VAL(3, SDRAM_PLB_M0ID_OPB)
72#define SDRAM_BESR_M0ID_MAL		PPC_REG_VAL(3, SDRAM_PLB_M0ID_MAL)
73#define SDRAM_BESR_M0ID_SEC		PPC_REG_VAL(3, SDRAM_PLB_M0ID_SEC)
74#define SDRAM_BESR_M0ID_AHB		PPC_REG_VAL(3, SDRAM_PLB_M0ID_AHB)
75#define SDRAM_BESR_M0ET_MASK		PPC_REG_VAL(6, 0x7)
76#define SDRAM_BESR_M0ET_NONE		PPC_REG_VAL(6, 0)
77#define SDRAM_BESR_M0ET_ECC		PPC_REG_VAL(6, 1)
78#define SDRAM_BESR_M0RW_MASK		PPC_REG_VAL(7, 1)
79#define SDRAM_BESR_M0RW_WRITE		PPC_REG_VAL(7, 0)
80#define SDRAM_BESR_M0RW_READ		PPC_REG_VAL(7, 1)
81
82/*
83 * Memory Controller PLB Write Master Interrupt Register
84 */
85#define SDRAM_WMIRQ_MASK		PPC_REG_VAL(8, 0x1FF)
86#define	SDRAM_WMIRQ_ENCODE(id)		PPC_REG_VAL((id % \
87						     SDRAM_PLB_M0ID_COUNT), 1)
88#define SDRAM_WMIRQ_ICU			PPC_REG_VAL(SDRAM_PLB_M0ID_ICU, 1)
89#define SDRAM_WMIRQ_PCIE0		PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE0, 1)
90#define SDRAM_WMIRQ_PCIE1		PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE1, 1)
91#define SDRAM_WMIRQ_DMA			PPC_REG_VAL(SDRAM_PLB_M0ID_DMA, 1)
92#define SDRAM_WMIRQ_DCU			PPC_REG_VAL(SDRAM_PLB_M0ID_DCU, 1)
93#define SDRAM_WMIRQ_OPB			PPC_REG_VAL(SDRAM_PLB_M0ID_OPB, 1)
94#define SDRAM_WMIRQ_MAL			PPC_REG_VAL(SDRAM_PLB_M0ID_MAL, 1)
95#define SDRAM_WMIRQ_SEC			PPC_REG_VAL(SDRAM_PLB_M0ID_SEC, 1)
96#define SDRAM_WMIRQ_AHB			PPC_REG_VAL(SDRAM_PLB_M0ID_AHB, 1)
97
98/*
99 * Memory Controller Options 1 Register
100 */
101#define SDRAM_MCOPT1_MCHK_MASK	    PPC_REG_VAL(3, 0x3)	 /* ECC mask	     */
102#define SDRAM_MCOPT1_MCHK_NON	    PPC_REG_VAL(3, 0x0)	 /* No ECC gen	     */
103#define SDRAM_MCOPT1_MCHK_GEN	    PPC_REG_VAL(3, 0x2)	 /* ECC gen	     */
104#define SDRAM_MCOPT1_MCHK_CHK	    PPC_REG_VAL(3, 0x1)	 /* ECC gen and chk  */
105#define SDRAM_MCOPT1_MCHK_CHK_REP   PPC_REG_VAL(3, 0x3)	 /* ECC gen/chk/rpt  */
106#define SDRAM_MCOPT1_MCHK_DECODE(n) ((((u32)(n)) >> 28) & 0x3)
107#define SDRAM_MCOPT1_RDEN_MASK	    PPC_REG_VAL(4, 0x1)	 /* Rgstrd DIMM mask */
108#define SDRAM_MCOPT1_RDEN	    PPC_REG_VAL(4, 0x1)	 /* Rgstrd DIMM enbl */
109#define SDRAM_MCOPT1_WDTH_MASK	    PPC_REG_VAL(7, 0x1)	 /* Width mask	     */
110#define SDRAM_MCOPT1_WDTH_32	    PPC_REG_VAL(7, 0x0)	 /* 32 bits	     */
111#define SDRAM_MCOPT1_WDTH_16	    PPC_REG_VAL(7, 0x1)	 /* 16 bits	     */
112#define SDRAM_MCOPT1_DDR_TYPE_MASK  PPC_REG_VAL(11, 0x1) /* DDR type mask    */
113#define SDRAM_MCOPT1_DDR1_TYPE	    PPC_REG_VAL(11, 0x0) /* DDR1 type	     */
114#define SDRAM_MCOPT1_DDR2_TYPE	    PPC_REG_VAL(11, 0x1) /* DDR2 type	     */
115
116/*
117 * Memory Bank 0 - n Configuration Register
118 */
119#define SDRAM_MBCF_BA_MASK		PPC_REG_VAL(12, 0x1FFF)
120#define SDRAM_MBCF_SZ_MASK		PPC_REG_VAL(19, 0xF)
121#define SDRAM_MBCF_SZ_DECODE(mbxcf)	PPC_REG_DECODE(19, mbxcf)
122#define SDRAM_MBCF_SZ_4MB		PPC_REG_VAL(19, 0x0)
123#define SDRAM_MBCF_SZ_8MB		PPC_REG_VAL(19, 0x1)
124#define SDRAM_MBCF_SZ_16MB		PPC_REG_VAL(19, 0x2)
125#define SDRAM_MBCF_SZ_32MB		PPC_REG_VAL(19, 0x3)
126#define SDRAM_MBCF_SZ_64MB		PPC_REG_VAL(19, 0x4)
127#define SDRAM_MBCF_SZ_128MB		PPC_REG_VAL(19, 0x5)
128#define SDRAM_MBCF_SZ_256MB		PPC_REG_VAL(19, 0x6)
129#define SDRAM_MBCF_SZ_512MB		PPC_REG_VAL(19, 0x7)
130#define SDRAM_MBCF_SZ_1GB		PPC_REG_VAL(19, 0x8)
131#define SDRAM_MBCF_SZ_2GB		PPC_REG_VAL(19, 0x9)
132#define SDRAM_MBCF_SZ_4GB		PPC_REG_VAL(19, 0xA)
133#define SDRAM_MBCF_SZ_8GB		PPC_REG_VAL(19, 0xB)
134#define SDRAM_MBCF_AM_MASK		PPC_REG_VAL(23, 0xF)
135#define SDRAM_MBCF_AM_MODE0		PPC_REG_VAL(23, 0x0)
136#define SDRAM_MBCF_AM_MODE1		PPC_REG_VAL(23, 0x1)
137#define SDRAM_MBCF_AM_MODE2		PPC_REG_VAL(23, 0x2)
138#define SDRAM_MBCF_AM_MODE3		PPC_REG_VAL(23, 0x3)
139#define SDRAM_MBCF_AM_MODE4		PPC_REG_VAL(23, 0x4)
140#define SDRAM_MBCF_AM_MODE5		PPC_REG_VAL(23, 0x5)
141#define SDRAM_MBCF_AM_MODE6		PPC_REG_VAL(23, 0x6)
142#define SDRAM_MBCF_AM_MODE7		PPC_REG_VAL(23, 0x7)
143#define SDRAM_MBCF_AM_MODE8		PPC_REG_VAL(23, 0x8)
144#define SDRAM_MBCF_AM_MODE9		PPC_REG_VAL(23, 0x9)
145#define SDRAM_MBCF_BE_MASK		PPC_REG_VAL(31, 0x1)
146#define SDRAM_MBCF_BE_DISABLE		PPC_REG_VAL(31, 0x0)
147#define SDRAM_MBCF_BE_ENABLE		PPC_REG_VAL(31, 0x1)
148
149/*
150 * ECC Error Status
151 */
152#define SDRAM_ECCES_MASK		PPC_REG_VAL(21, 0x3FFFFF)
153#define SDRAM_ECCES_BNCE_MASK		PPC_REG_VAL(15, 0xFFFF)
154#define SDRAM_ECCES_BNCE_ENCODE(lane)	PPC_REG_VAL(((lane) & 0xF), 1)
155#define SDRAM_ECCES_CKBER_MASK		PPC_REG_VAL(17, 0x3)
156#define SDRAM_ECCES_CKBER_NONE		PPC_REG_VAL(17, 0)
157#define SDRAM_ECCES_CKBER_16_ECC_0_3	PPC_REG_VAL(17, 2)
158#define SDRAM_ECCES_CKBER_32_ECC_0_3	PPC_REG_VAL(17, 1)
159#define SDRAM_ECCES_CKBER_32_ECC_4_8	PPC_REG_VAL(17, 2)
160#define SDRAM_ECCES_CKBER_32_ECC_0_8	PPC_REG_VAL(17, 3)
161#define SDRAM_ECCES_CE			PPC_REG_VAL(18, 1)
162#define SDRAM_ECCES_UE			PPC_REG_VAL(19, 1)
163#define SDRAM_ECCES_BKNER_MASK		PPC_REG_VAL(21, 0x3)
164#define SDRAM_ECCES_BK0ER		PPC_REG_VAL(20, 1)
165#define SDRAM_ECCES_BK1ER		PPC_REG_VAL(21, 1)
166
167#endif /* __PPC4XX_EDAC_H */
168