Searched refs:x1 (Results 26 - 50 of 5701) sorted by relevance

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/linux-master/sound/soc/codecs/
H A Drt5677.h298 #define RT5677_L_MUTE (0x1 << 15)
300 #define RT5677_VOL_L_MUTE (0x1 << 14)
302 #define RT5677_R_MUTE (0x1 << 7)
304 #define RT5677_VOL_R_MUTE (0x1 << 6)
312 #define RT5677_LOUT1_L_MUTE (0x1 << 15)
314 #define RT5677_LOUT1_L_DF (0x1 << 14)
316 #define RT5677_LOUT2_L_MUTE (0x1 << 13)
318 #define RT5677_LOUT2_L_DF (0x1 << 12)
320 #define RT5677_LOUT3_L_MUTE (0x1 << 11)
322 #define RT5677_LOUT3_L_DF (0x1 << 1
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H A Drt5665.h431 #define RT5665_L_MUTE (0x1 << 15)
433 #define RT5665_VOL_L_MUTE (0x1 << 14)
435 #define RT5665_R_MUTE (0x1 << 7)
437 #define RT5665_VOL_R_MUTE (0x1 << 6)
455 #define RT5665_IN1_DF_MASK (0x1 << 15)
459 #define RT5665_IN2_DF_MASK (0x1 << 7)
465 #define RT5665_IN3_DF_MASK (0x1 << 15)
469 #define RT5665_IN4_DF_MASK (0x1 << 7)
481 #define RT5665_EMB_JD_EN (0x1 << 15)
483 #define RT5665_JD_MODE (0x1 << 1
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H A Drt1016.h78 #define RT1016_CLK_SYS_SEL_MASK (0x1 << 15)
81 #define RT1016_CLK_SYS_SEL_PLL (0x1 << 15)
82 #define RT1016_PLL_SEL_MASK (0x1 << 13)
85 #define RT1016_PLL_SEL_BCLK (0x1 << 13)
94 #define RT1016_PWR_DAC_FILTER (0x1 << 11)
96 #define RT1016_PWR_DACMOD (0x1 << 10)
98 #define RT1016_PWR_CLK_FIFO (0x1 << 9)
100 #define RT1016_PWR_CLK_PUREDC (0x1 << 8)
102 #define RT1016_PWR_SIL_DET (0x1 << 7)
104 #define RT1016_PWR_RC_25M (0x1 <<
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H A Drt5682s.h412 #define RT5682S_L_MUTE (0x1 << 15)
414 #define RT5682S_R_MUTE (0x1 << 7)
419 #define RT5682S_CLK_SRC_PLL1 (0x1)
425 #define RT5682S_HPO_L_PATH_MASK (0x1 << 14)
426 #define RT5682S_HPO_L_PATH_EN (0x1 << 14)
428 #define RT5682S_HPO_R_PATH_MASK (0x1 << 13)
429 #define RT5682S_HPO_R_PATH_EN (0x1 << 13)
431 #define RT5682S_HPO_SEL_IP_EN_SW (0x1)
432 #define RT5682S_HPO_IP_EN_GATING (0x1)
442 #define RT5682S_EMB_JD_MASK (0x1 << 1
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H A Drt5682.h366 #define RT5682_L_MUTE (0x1 << 15)
368 #define RT5682_VOL_L_MUTE (0x1 << 14)
370 #define RT5682_R_MUTE (0x1 << 7)
372 #define RT5682_VOL_R_MUTE (0x1 << 6)
381 #define RT5682_HP_C2_DAC_AMP_MUTE (0x1 << 15)
383 #define RT5682_HP_C2_DAC_L_EN (0x1 << 14)
385 #define RT5682_HP_C2_DAC_R_EN (0x1 << 13)
398 #define RT5682_EMB_JD_EN (0x1 << 15)
400 #define RT5682_EMB_JD_RST (0x1 << 14)
401 #define RT5682_JD_MODE (0x1 << 1
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H A Dinno_rk3036.h26 #define INNO_R00_CSR_WORK (0x1 << 0)
28 #define INNO_R00_CDCR_WORK (0x1 << 1)
30 #define INNO_R00_PRB_ENABLE (0x1 << 6)
32 #define INNO_R01_I2SMODE_MSK (0x1 << 4)
34 #define INNO_R01_I2SMODE_MASTER (0x1 << 4)
35 #define INNO_R01_PINDIR_MSK (0x1 << 5)
37 #define INNO_R01_PINDIR_OUT_MASTER (0x1 << 5)
39 #define INNO_R02_LRS_MSK (0x1 << 2)
41 #define INNO_R02_LRS_SWAP (0x1 << 2)
45 #define INNO_R02_DACM_LJM (0x1 <<
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/linux-master/drivers/gpu/drm/radeon/
H A Drs400d.h47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
50 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
51 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
53 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
54 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
56 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
57 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
59 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
60 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
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H A Drs690d.h39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1)
55 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
56 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
58 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
59 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
61 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
62 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
64 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
65 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
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H A Dr300d.h92 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
93 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
95 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
96 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
98 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
99 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
101 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
102 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
104 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
105 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/smuio/
H A Dsmuio_12_0_0_sh_mask.h26 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
29 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
/linux-master/drivers/media/pci/cobalt/
H A Dm00233_video_measure_memmap_package.h54 #define M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_OFST)
56 #define M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_OFST)
58 #define M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_OFST)
60 #define M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_OFST)
62 #define M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_OFST)
64 #define M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_OFST)
66 #define M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_OFST)
68 #define M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_OFST)
71 #define M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK (0x1 << M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST)
73 #define M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK (0x1 << M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFS
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H A Dm00389_cvi_memmap_package.h36 #define M00389_CONTROL_BITMAP_ENABLE_MSK (0x1 << M00389_CONTROL_BITMAP_ENABLE_OFST)
38 #define M00389_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK (0x1 << M00389_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST)
40 #define M00389_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK (0x1 << M00389_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST)
43 #define M00389_STATUS_BITMAP_LOCK_MSK (0x1 << M00389_STATUS_BITMAP_LOCK_OFST)
45 #define M00389_STATUS_BITMAP_ERROR_MSK (0x1 << M00389_STATUS_BITMAP_ERROR_OFST)
/linux-master/drivers/infiniband/hw/qib/
H A Dqib_6120_regs.h37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
53 #define QIB_6120_Control_TxLatency_RMASK 0x1
55 #define QIB_6120_Control_PCIERetryBufDiagEn_RMASK 0x1
57 #define QIB_6120_Control_LinkEn_RMASK 0x1
58 #define QIB_6120_Control_FreezeMode_LSB 0x1
59 #define QIB_6120_Control_FreezeMode_RMASK 0x1
61 #define QIB_6120_Control_SyncReset_RMASK 0x1
81 #define QIB_6120_IntBlocked_ErrorIntBlocked_RMASK 0x1
83 #define QIB_6120_IntBlocked_PioSetIntBlocked_RMASK 0x1
85 #define QIB_6120_IntBlocked_PioBufAvailIntBlocked_RMASK 0x1
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/linux-master/drivers/extcon/
H A Dextcon-rt8973a.h17 RT8973A_REG_DEVICE_ID = 0x1,
61 #define RT8973A_REG_CONTROL1_INTM_MASK (0x1 << RT8973A_REG_CONTROL1_INTM_SHIFT)
62 #define RT8973A_REG_CONTROL1_AUTO_CONFIG_MASK (0x1 << RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT)
63 #define RT8973A_REG_CONTROL1_I2C_RST_EN_MASK (0x1 << RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT)
64 #define RT8973A_REG_CONTROL1_SWITCH_OPEN_MASK (0x1 << RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT)
65 #define RT8973A_REG_CONTROL1_CHGTYP_MASK (0x1 << RT8973A_REG_CONTROL1_CHGTYP_SHIFT)
66 #define RT8973A_REG_CONTROL1_USB_CHD_EN_MASK (0x1 << RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT)
67 #define RT8973A_REG_CONTROL1_ADC_EN_MASK (0x1 << RT8973A_REG_CONTROL1_ADC_EN_SHIFT)
77 #define RT9873A_REG_INTM1_ATTACH_MASK (0x1 << RT9873A_REG_INTM1_ATTACH_SHIFT)
78 #define RT9873A_REG_INTM1_DETACH_MASK (0x1 << RT9873A_REG_INTM1_DETACH_SHIF
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/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_hw_20_comp_defs.h7 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK 0x1
11 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE = 0x1,
18 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK 0x1
22 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_FC_ONLY = 0x1,
33 ICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE = 0x1,
42 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK 0x1
46 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1,
53 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK 0x1
57 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_NO_UNLOAD = 0x1,
64 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK 0x1
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/linux-master/tools/perf/util/
H A Ddemangle-java.h7 #define JAVA_DEMANGLE_NORET 0x1 /* do not process return type */
/linux-master/include/dt-bindings/phy/
H A Dphy-pistachio-usb.h10 #define REFCLK_X0_EXT_CLK 0x1
/linux-master/scripts/dtc/include-prefixes/dt-bindings/phy/
H A Dphy-pistachio-usb.h10 #define REFCLK_X0_EXT_CLK 0x1
/linux-master/include/dt-bindings/sound/
H A Dcs35l45.h17 #define CS35L45_ASP_TX_HIZ_UNUSED 0x1
/linux-master/scripts/dtc/include-prefixes/dt-bindings/sound/
H A Dcs35l45.h17 #define CS35L45_ASP_TX_HIZ_UNUSED 0x1
/linux-master/include/uapi/linux/
H A Dconnector.h31 #define CN_IDX_PROC 0x1
32 #define CN_VAL_PROC 0x1
34 #define CN_VAL_CIFS 0x1
36 #define CN_W1_VAL 0x1
38 #define CN_VAL_V86D_UVESAFB 0x1
41 #define CN_DST_VAL 0x1
43 #define CN_VAL_DM_USERSPACE_LOG 0x1
45 #define CN_VAL_DRBD 0x1
47 #define CN_KVP_VAL 0x1 /* queries from the kernel */
49 #define CN_VSS_VAL 0x1 /* querie
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/linux-master/include/linux/mtd/
H A Dsh_flctl.h41 #define _4ECCCNTEN (0x1 << 24)
42 #define _4ECCEN (0x1 << 23)
43 #define _4ECCCORRECT (0x1 << 22)
44 #define SHBUSSEL (0x1 << 20)
45 #define SEL_16BIT (0x1 << 19)
46 #define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/
47 #define QTSEL_E (0x1 << 17)
48 #define ENDIAN (0x1 << 16) /* 1 = little endian */
49 #define FCKSEL_E (0x1 << 15)
51 #define NANWF_E (0x1 <<
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/linux-master/sound/soc/atmel/
H A Datmel-classd.h6 #define CLASSD_CR_RESET 0x1
11 #define CLASSD_MR_LEN_EN 0x1
12 #define CLASSD_MR_LEN_MASK (0x1 << 0)
16 #define CLASSD_MR_LMUTE_EN 0x1
17 #define CLASSD_MR_LMUTE_SHIFT (0x1)
18 #define CLASSD_MR_LMUTE_MASK (0x1 << 1)
21 #define CLASSD_MR_REN_EN 0x1
22 #define CLASSD_MR_REN_MASK (0x1 << 4)
26 #define CLASSD_MR_RMUTE_EN 0x1
28 #define CLASSD_MR_RMUTE_MASK (0x1 <<
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/linux-master/arch/arm64/boot/dts/ti/
H A Dk3-serdes.h14 #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
19 #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
24 #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
29 #define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
34 #define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
39 #define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
44 #define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
49 #define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
54 #define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
59 #define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
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/linux-master/scripts/dtc/include-prefixes/arm64/ti/
H A Dk3-serdes.h14 #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
19 #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
24 #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
29 #define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
34 #define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
39 #define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
44 #define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
49 #define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
54 #define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
59 #define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
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