1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright(c) 2022 Intel Corporation */ 3#ifndef _ICP_QAT_HW_20_COMP_DEFS_H 4#define _ICP_QAT_HW_20_COMP_DEFS_H 5 6#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS 31 7#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK 0x1 8 9enum icp_qat_hw_comp_20_scb_control { 10 ICP_QAT_HW_COMP_20_SCB_CONTROL_ENABLE = 0x0, 11 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE = 0x1, 12}; 13 14#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_DEFAULT_VAL \ 15 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE 16 17#define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS 30 18#define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK 0x1 19 20enum icp_qat_hw_comp_20_rmb_control { 21 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL = 0x0, 22 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_FC_ONLY = 0x1, 23}; 24 25#define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_DEFAULT_VAL \ 26 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL 27 28#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS 28 29#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK 0x3 30 31enum icp_qat_hw_comp_20_som_control { 32 ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE = 0x0, 33 ICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE = 0x1, 34 ICP_QAT_HW_COMP_20_SOM_CONTROL_INPUT_CRC = 0x2, 35 ICP_QAT_HW_COMP_20_SOM_CONTROL_RESERVED_MODE = 0x3, 36}; 37 38#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL \ 39 ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE 40 41#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS 27 42#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK 0x1 43 44enum icp_qat_hw_comp_20_skip_hash_rd_control { 45 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0, 46 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1, 47}; 48 49#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL \ 50 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP 51 52#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS 26 53#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK 0x1 54 55enum icp_qat_hw_comp_20_scb_unload_control { 56 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD = 0x0, 57 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_NO_UNLOAD = 0x1, 58}; 59 60#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_DEFAULT_VAL \ 61 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD 62 63#define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS 21 64#define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK 0x1 65 66enum icp_qat_hw_comp_20_disable_token_fusion_control { 67 ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE = 0x0, 68 ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_DISABLE = 0x1, 69}; 70 71#define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_DEFAULT_VAL \ 72 ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE 73 74#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS 19 75#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK 0x3 76 77enum icp_qat_hw_comp_20_lbms { 78 ICP_QAT_HW_COMP_20_LBMS_LBMS_64KB = 0x0, 79 ICP_QAT_HW_COMP_20_LBMS_LBMS_256KB = 0x1, 80 ICP_QAT_HW_COMP_20_LBMS_LBMS_1MB = 0x2, 81 ICP_QAT_HW_COMP_20_LBMS_LBMS_4MB = 0x3, 82}; 83 84#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL \ 85 ICP_QAT_HW_COMP_20_LBMS_LBMS_64KB 86 87#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS 18 88#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK 0x1 89 90enum icp_qat_hw_comp_20_scb_mode_reset_mask { 91 ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS = 0x0, 92 ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS_AND_HISTORY = 0x1, 93}; 94 95#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL \ 96 ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS 97 98#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS 9 99#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK 0x1ff 100#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL 258 101 102#define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS 0 103#define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK 0x1ff 104#define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL 259 105 106#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS 14 107#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK 0x7 108 109enum icp_qat_hw_comp_20_hbs_control { 110 ICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_32KB = 0x0, 111 ICP_QAT_HW_COMP_23_HBS_CONTROL_HBS_IS_64KB = 0x1, 112}; 113 114#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL \ 115 ICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_32KB 116 117#define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS 13 118#define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK 0x1 119 120enum icp_qat_hw_comp_20_abd { 121 ICP_QAT_HW_COMP_20_ABD_ABD_ENABLED = 0x0, 122 ICP_QAT_HW_COMP_20_ABD_ABD_DISABLED = 0x1, 123}; 124 125#define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_DEFAULT_VAL \ 126 ICP_QAT_HW_COMP_20_ABD_ABD_ENABLED 127 128#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS 12 129#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK 0x1 130 131enum icp_qat_hw_comp_20_lllbd_ctrl { 132 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED = 0x0, 133 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_DISABLED = 0x1, 134}; 135 136#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_DEFAULT_VAL \ 137 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED 138 139#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS 8 140#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK 0xf 141 142enum icp_qat_hw_comp_20_search_depth { 143 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1 = 0x1, 144 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_6 = 0x3, 145 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_9 = 0x4, 146}; 147 148#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_DEFAULT_VAL \ 149 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1 150 151#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS 5 152#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK 0x7 153 154enum icp_qat_hw_comp_20_hw_comp_format { 155 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77 = 0x0, 156 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE = 0x1, 157 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_LZ4 = 0x2, 158 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_LZ4S = 0x3, 159 ICP_QAT_HW_COMP_23_HW_COMP_FORMAT_ZSTD = 0x4, 160}; 161 162#define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_DEFAULT_VAL \ 163 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE 164 165#define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS 4 166#define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK 0x1 167 168enum icp_qat_hw_comp_20_min_match_control { 169 ICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_3B = 0x0, 170 ICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_4B = 0x1, 171}; 172 173#define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL \ 174 ICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_3B 175 176#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS 3 177#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK 0x1 178 179enum icp_qat_hw_comp_20_skip_hash_collision { 180 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_ALLOW = 0x0, 181 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_DONT_ALLOW = 0x1, 182}; 183 184#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_DEFAULT_VAL \ 185 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_ALLOW 186 187#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS 2 188#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK 0x1 189 190enum icp_qat_hw_comp_20_skip_hash_update { 191 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_ALLOW = 0x0, 192 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW = 0x1, 193}; 194 195#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_DEFAULT_VAL \ 196 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_ALLOW 197 198#define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS 1 199#define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK 0x1 200 201enum icp_qat_hw_comp_20_byte_skip { 202 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_TOKEN = 0x0, 203 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL = 0x1, 204}; 205 206#define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_DEFAULT_VAL \ 207 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_TOKEN 208 209#define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS 0 210#define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK 0x1 211 212enum icp_qat_hw_comp_20_extended_delay_match_mode { 213 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_DISABLED = 0x0, 214 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED = 0x1, 215}; 216 217#define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_DEFAULT_VAL \ 218 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_DISABLED 219 220#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS 31 221#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK 0x1 222 223enum icp_qat_hw_decomp_20_speculative_decoder_control { 224 ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_ENABLE = 0x0, 225 ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_DISABLE = 0x1, 226}; 227 228#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_DEFAULT_VAL \ 229 ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_ENABLE 230 231#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS 30 232#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK 0x1 233 234enum icp_qat_hw_decomp_20_mini_cam_control { 235 ICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_ENABLE = 0x0, 236 ICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_DISABLE = 0x1, 237}; 238 239#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_DEFAULT_VAL \ 240 ICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_ENABLE 241 242#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS 14 243#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK 0x7 244 245enum icp_qat_hw_decomp_20_hbs_control { 246 ICP_QAT_HW_DECOMP_20_HBS_CONTROL_HBS_IS_32KB = 0x0, 247}; 248 249#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL \ 250 ICP_QAT_HW_DECOMP_20_HBS_CONTROL_HBS_IS_32KB 251 252#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS 8 253#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK 0x3 254 255enum icp_qat_hw_decomp_20_lbms { 256 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_64KB = 0x0, 257 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_256KB = 0x1, 258 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_1MB = 0x2, 259 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_4MB = 0x3, 260}; 261 262#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL \ 263 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_64KB 264 265#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS 5 266#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK 0x7 267 268enum icp_qat_hw_decomp_20_hw_comp_format { 269 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE = 0x1, 270 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_LZ4 = 0x2, 271 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_LZ4S = 0x3, 272 ICP_QAT_HW_DECOMP_23_HW_DECOMP_FORMAT_ZSTD = 0x4, 273}; 274 275#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_DEFAULT_VAL \ 276 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE 277 278#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS 4 279#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK 0x1 280 281enum icp_qat_hw_decomp_20_min_match_control { 282 ICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_3B = 0x0, 283 ICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_4B = 0x1, 284}; 285 286#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL \ 287 ICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_3B 288 289#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS 3 290#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK 0x1 291 292enum icp_qat_hw_decomp_20_lz4_block_checksum_present { 293 ICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_ABSENT = 0x0, 294 ICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_PRESENT = 0x1, 295}; 296 297#define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_DEFAULT_VAL \ 298 ICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_ABSENT 299 300#endif 301