Searched refs:vmid (Results 26 - 50 of 224) sorted by relevance

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/linux-master/arch/riscv/include/asm/
H A Dkvm_host.h96 * Writes to vmid_version and vmid happen with vmid_lock held
100 unsigned long vmid; member in struct:kvm_vmid
104 /* G-stage vmid */
105 struct kvm_vmid vmid; member in struct:kvm_arch
293 void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid,
296 void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid);
300 void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid,
305 void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid,
307 void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid,
310 void kvm_riscv_local_hfence_vvma_all(unsigned long vmid);
[all...]
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v10.c45 uint32_t queue, uint32_t vmid)
48 nv_grbm_select(adev, mec, pipe, queue, vmid);
80 static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid, argument
86 lock_srbm(adev, 0, 0, 0, vmid);
96 unsigned int vmid, uint32_t inst)
108 pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping);
110 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
111 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
119 (1U << vmid)))
44 lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, uint32_t queue, uint32_t vmid) argument
95 kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid, unsigned int vmid, uint32_t inst) argument
665 get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, uint8_t vmid, uint16_t *p_pasid) argument
701 set_vm_context_page_table_base(struct amdgpu_device *adev, uint32_t vmid, uint64_t page_table_base) argument
736 kgd_gfx_v10_set_wave_launch_stall(struct amdgpu_device *adev, uint32_t vmid, bool stall) argument
753 kgd_gfx_v10_enable_debug_trap(struct amdgpu_device *adev, bool restore_dbg_registers, uint32_t vmid) argument
790 kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev, bool keep_trap_enabled, uint32_t vmid) argument
825 kgd_gfx_v10_set_wave_launch_trap_override(struct amdgpu_device *adev, uint32_t vmid, uint32_t trap_override, uint32_t trap_mask_bits, uint32_t trap_mask_request, uint32_t *trap_mask_prev, uint32_t kfd_dbg_trap_cntl_prev) argument
859 kgd_gfx_v10_set_wave_launch_mode(struct amdgpu_device *adev, uint8_t wave_launch_mode, uint32_t vmid) argument
1047 program_trap_handler_settings(struct amdgpu_device *adev, uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, uint32_t inst) argument
[all...]
H A Dvcn_v2_0.h37 unsigned vmid, uint64_t pd_addr);
50 unsigned int vmid, uint64_t pd_addr);
H A Damdgpu_umr.h34 __u32 me, pipe, queue, vmid; member in struct:amdgpu_debugfs_regs2_iocdata::__anon159
44 __u32 me, pipe, queue, vmid; member in struct:amdgpu_debugfs_regs2_iocdata_v2::__anon161
H A Damdgpu_gmc.h92 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type);
130 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
137 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
140 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
350 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
351 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
415 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
H A Damdgpu_amdkfd_aldebaran.c42 uint32_t vmid)
56 uint32_t vmid)
90 uint32_t vmid,
113 uint32_t vmid)
40 kgd_aldebaran_enable_debug_trap(struct amdgpu_device *adev, bool restore_dbg_registers, uint32_t vmid) argument
54 kgd_aldebaran_disable_debug_trap(struct amdgpu_device *adev, bool keep_trap_enabled, uint32_t vmid) argument
89 kgd_aldebaran_set_wave_launch_trap_override(struct amdgpu_device *adev, uint32_t vmid, uint32_t trap_override, uint32_t trap_mask_bits, uint32_t trap_mask_request, uint32_t *trap_mask_prev, uint32_t kfd_dbg_trap_cntl_prev) argument
111 kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev, uint8_t wave_launch_mode, uint32_t vmid) argument
H A Damdgpu_amdkfd_gfx_v8.c43 uint32_t queue, uint32_t vmid)
45 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
71 static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid, argument
77 lock_srbm(adev, 0, 0, 0, vmid);
88 unsigned int vmid, uint32_t inst)
100 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
102 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
104 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
106 /* Mapping vmid to pasid also for IH block */
107 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mappin
42 lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, uint32_t queue, uint32_t vmid) argument
87 kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid, unsigned int vmid, uint32_t inst) argument
531 get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, uint8_t vmid, uint16_t *p_pasid) argument
566 set_scratch_backing_va(struct amdgpu_device *adev, uint64_t va, uint32_t vmid) argument
574 set_vm_context_page_table_base(struct amdgpu_device *adev, uint32_t vmid, uint64_t page_table_base) argument
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H A Damdgpu_job.h42 #define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
59 unsigned vmid; member in struct:amdgpu_job
H A Dgmc_v10_0.c161 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n",
163 entry->src_id, entry->ring_id, entry->vmid, entry->pasid);
221 uint8_t vmid, uint16_t *p_pasid)
226 + vmid);
243 * @vmid: vm instance to flush
249 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, argument
254 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
275 1 << vmid, GET_INST(GC, 0));
317 tmp &= 1 << vmid;
351 int vmid, local
219 gmc_v10_0_get_atc_vmid_pasid_mapping_info( struct amdgpu_device *adev, uint8_t vmid, uint16_t *p_pasid) argument
373 gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, unsigned int vmid, uint64_t pd_addr) argument
421 gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, unsigned int pasid) argument
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H A Dgmc_v11_0.c132 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n",
134 entry->src_id, entry->ring_id, entry->vmid, entry->pasid);
191 uint8_t vmid, uint16_t *p_pasid)
193 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
202 * @vmid: vm instance to flush
208 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, argument
213 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
237 1 << vmid, GET_INST(GC, 0));
271 tmp &= 1 << vmid;
317 int vmid, local
189 gmc_v11_0_get_vmid_pasid_mapping_info( struct amdgpu_device *adev, uint8_t vmid, uint16_t *p_pasid) argument
339 gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, unsigned int vmid, uint64_t pd_addr) argument
387 gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, unsigned int pasid) argument
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H A Damdgpu_trace.h84 __field(unsigned, vmid)
96 __entry->vmid = iv->vmid;
106 TP_printk("ih:%u client_id:%u src_id:%u ring:%u vmid:%u "
109 __entry->ring_id, __entry->vmid,
226 __field(u32, vmid)
235 __entry->vmid = job->vmid;
241 __entry->pasid, __get_str(ring), __entry->vmid,
417 TP_PROTO(struct amdgpu_ring *ring, unsigned vmid,
[all...]
H A Damdgpu_amdkfd_gfx_v10_3.c45 uint32_t queue, uint32_t vmid)
48 nv_grbm_select(adev, mec, pipe, queue, vmid);
80 static void program_sh_mem_settings_v10_3(struct amdgpu_device *adev, uint32_t vmid, argument
86 lock_srbm(adev, 0, 0, 0, vmid);
97 unsigned int vmid, uint32_t inst)
101 /* Mapping vmid to pasid also for IH block */
102 pr_debug("mapping vmid %d -> pasid %d in IH block for GFX client\n",
103 vmid, pasid);
104 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, value);
193 /* HIQ is set during driver init period with vmid se
44 lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, uint32_t queue, uint32_t vmid) argument
96 set_pasid_vmid_mapping_v10_3(struct amdgpu_device *adev, unsigned int pasid, unsigned int vmid, uint32_t inst) argument
613 get_atc_vmid_pasid_mapping_info_v10_3(struct amdgpu_device *adev, uint8_t vmid, uint16_t *p_pasid) argument
625 set_vm_context_page_table_base_v10_3(struct amdgpu_device *adev, uint32_t vmid, uint64_t page_table_base) argument
632 program_trap_handler_settings_v10_3(struct amdgpu_device *adev, uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, uint32_t inst) argument
[all...]
H A Damdgpu_amdkfd_arcturus.c351 uint32_t vmid)
355 kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);
361 kgd_gfx_v9_set_wave_launch_stall(adev, vmid, false);
376 uint32_t vmid)
381 kgd_gfx_v9_set_wave_launch_stall(adev, vmid, true);
387 kgd_gfx_v9_set_wave_launch_stall(adev, vmid, false);
349 kgd_arcturus_enable_debug_trap(struct amdgpu_device *adev, bool restore_dbg_registers, uint32_t vmid) argument
374 kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev, bool keep_trap_enabled, uint32_t vmid) argument
H A Damdgpu_amdkfd_gc_9_4_3.c224 u32 pasid, unsigned int vmid, uint32_t xcc_inst)
243 regATC_VMID0_PASID_MAPPING) + vmid, pasid_mapping);
248 (1U << vmid))) {
258 1U << vmid); local
268 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid,
272 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid,
365 uint32_t vmid)
438 uint32_t vmid,
223 kgd_gfx_v9_4_3_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid, unsigned int vmid, uint32_t xcc_inst) argument
363 kgd_gfx_v9_4_3_disable_debug_trap(struct amdgpu_device *adev, bool keep_trap_enabled, uint32_t vmid) argument
436 kgd_gfx_v9_4_3_set_wave_launch_trap_override( struct amdgpu_device *adev, uint32_t vmid, uint32_t trap_override, uint32_t trap_mask_bits, uint32_t trap_mask_request, uint32_t *trap_mask_prev, uint32_t kfd_dbg_trap_cntl_prev) argument
H A Dvpe_6_1_fw_if.h186 #define VPE_CMD_INDIRECT_HEADER_VMID(vmid) \
187 (((vmid) & VPE_CMD_INDIRECT_HEADER_VMID_MASK) << VPE_CMD_INDIRECT_HEADER_VMID__SHIFT)
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_queue.c39 pr_debug("Queue Process Vmid: %u\n", q->vmid);
56 pr_debug("Queue Process Vmid: %u\n", q->properties.vmid);
H A Dkfd_int_process_v9.c221 uint16_t source_id, client_id, pasid, vmid; local
228 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
230 (vmid < dev->vm_info.first_vmid_kfd ||
231 vmid > dev->vm_info.last_vmid_kfd))
267 pasid = dev->dqm->vmid_pasid[vmid];
274 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",
275 client_id, source_id, vmid, pasid);
316 uint16_t source_id, client_id, pasid, vmid; local
323 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
440 info.vmid
473 uint16_t node_id, vmid; local
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H A Dkfd_int_process_v11.c238 uint16_t source_id, client_id, pasid, vmid; local
245 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
247 (vmid < dev->vm_info.first_vmid_kfd ||
248 vmid > dev->vm_info.last_vmid_kfd))
258 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",
259 client_id, source_id, vmid, pasid);
285 uint16_t source_id, client_id, ring_id, pasid, vmid; local
295 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
304 info.vmid = vmid;
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H A Dkfd_int_process_v10.c194 uint16_t source_id, client_id, pasid, vmid; local
201 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
203 (vmid < dev->vm_info.first_vmid_kfd ||
204 vmid > dev->vm_info.last_vmid_kfd))
228 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",
229 client_id, source_id, vmid, pasid);
254 uint16_t source_id, client_id, pasid, vmid; local
261 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
397 info.vmid = vmid;
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/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_vm_helper.c56 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid) argument
58 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid);
/linux-master/drivers/virt/acrn/
H A Dmm.c28 regions->vmid = vm->vmid;
35 "Failed to set memory region for VM[%u]!\n", vm->vmid);
126 "Add memory region failed, VM[%u]!\n", vm->vmid);
144 "Del memory region failed, VM[%u]!\n", vm->vmid);
296 regions_info->vmid = vm->vmid;
321 "Failed to set regions, VM[%u]!\n", vm->vmid);
328 __func__, vm->vmid,
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_trace.h51 TP_PROTO(unsigned vmid, int ring),
52 TP_ARGS(vmid, ring),
54 __field(u32, vmid)
59 __entry->vmid = vmid;
62 TP_printk("vmid=%u, ring=%u", __entry->vmid, __entry->ring)
/linux-master/drivers/soc/qcom/
H A Drmtfs_mem.c178 u32 vmid[NUM_MAX_VMIDS]; local
239 num_vmids = of_property_count_u32_elems(node, "qcom,vmid");
241 /* qcom,vmid is optional */
244 dev_err(&pdev->dev, "failed to count qcom,vmid elements: %d\n", num_vmids);
254 ret = of_property_read_u32_array(node, "qcom,vmid", vmid, num_vmids);
256 dev_err(&pdev->dev, "failed to parse qcom,vmid\n");
264 perms[0].vmid = QCOM_SCM_VMID_HLOS;
268 perms[i + 1].vmid = vmid[
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.h90 struct dcn20_vmid vmid[16]; member in struct:dcn20_hubbub
129 int vmid);
/linux-master/arch/riscv/kvm/
H A DMakefile14 kvm-y += vmid.o

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