Searched refs:stage (Results 101 - 125 of 149) sorted by relevance

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/linux-master/drivers/usb/renesas_usbhs/
H A Dmod_gadget.c485 int stage = usbhs_status_get_ctrl_stage(irq_state); local
488 dev_dbg(dev, "stage = %d\n", stage);
499 switch (stage) {
538 * setup stage / run recip
/linux-master/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_init_ops.h229 static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage) argument
232 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
235 INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
322 * this is done as a separate init stage.
834 * called during init common stage, ilt clients should be initialized
856 /* called during init port stage */
888 /* called during init common stage */
914 /* called during init func stage */
/linux-master/drivers/staging/media/atomisp/pci/
H A Dsh_css.c1195 struct ia_css_pipeline_stage *stage; local
1197 stage = me->pipeline.stages;
1198 if (stage) {
1199 me->pipeline.current_stage = stage;
1200 start_binary(me, stage->binary);
3477 struct ia_css_pipeline_stage *stage; local
3606 for (stage = pipeline->stages; stage; stage = stage
7367 struct ia_css_pipeline_stage *stage; local
[all...]
/linux-master/drivers/video/fbdev/
H A Dimsttfb.c438 __u32 clk_m, clk_n, x, stage, spilled; local
441 stage = spilled = 0;
443 switch (stage) {
456 stage = 1;
458 stage = 0;
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8192c/
H A Dphy_common.c778 u8 channel, u8 *stage, u8 *step,
819 switch (*stage) {
830 pr_err("Invalid 'stage' = %d, Check it!\n",
831 *stage);
836 if ((*stage) == 2) {
839 (*stage)++;
777 _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel, u8 *stage, u8 *step, u32 *delay) argument
/linux-master/drivers/infiniband/hw/mlx5/
H A Dmain.c897 /* At this stage no support for signature handover */
2908 * At this stage, the mlx5_ib_event should be unregistered
4184 int stage)
4189 while (stage) {
4190 stage--;
4191 if (profile->stage[stage].cleanup)
4192 profile->stage[stage].cleanup(dev);
4208 if (profile->stage[
4182 __mlx5_ib_remove(struct mlx5_ib_dev *dev, const struct mlx5_ib_profile *profile, int stage) argument
[all...]
H A Dmlx5_ib.h979 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
982 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; member in struct:mlx5_ib_profile
1463 int stage);
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dphy.c31 u8 channel, u8 *stage, u8 *step,
1212 u8 channel, u8 *stage, u8 *step,
1253 switch (*stage) {
1264 pr_err("Invalid 'stage' = %d, Check it!\n",
1265 *stage);
1270 if ((*stage) == 2)
1272 (*stage)++;
1211 _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel, u8 *stage, u8 *step, u32 *delay) argument
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dphy.c25 u8 channel, u8 *stage,
1338 u8 channel, u8 *stage,
1382 switch (*stage) {
1393 pr_err("Invalid 'stage' = %d, Check it!\n",
1394 *stage);
1399 if ((*stage) == 2) {
1402 (*stage)++;
1337 _rtl8723be_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel, u8 *stage, u8 *step, u32 *delay) argument
/linux-master/drivers/md/dm-vdo/indexer/
H A Dindex.c44 * during the triage stage that acts as a rendezvous. Once every zone has reached the barrier and
1359 void uds_enqueue_request(struct uds_request *request, enum request_stage stage) argument
1364 switch (stage) {
1383 VDO_ASSERT_LOG_ONLY(false, "invalid index stage: %d", stage);
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_plane.c834 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos;
835 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
1265 drm_printf(p, "\tstage=%d\n", pstate->stage);
H A Ddpu_hw_ctl.c514 enum dpu_sspp pipe = stage_cfg->stage[i][j];
/linux-master/tools/testing/selftests/kvm/s390x/
H A Dmemop.c259 enum stage { enum
272 #define HOST_SYNC(info_p, stage) \
277 int __stage = (stage); \
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dphy.c311 u8 channel, u8 *stage, u8 *step, u32 *delay)
349 switch (*stage) {
364 if ((*stage) == 2) {
367 (*stage)++;
310 _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel, u8 *stage, u8 *step, u32 *delay) argument
/linux-master/drivers/md/dm-vdo/
H A Ddata-vio.h106 enum data_vio_compression_stage stage; member in struct:data_vio_compression_status
/linux-master/drivers/ufs/host/
H A Dufs-mediatek.c1134 enum ufs_notify_change_status stage,
1140 switch (stage) {
1235 enum ufs_notify_change_status stage)
1239 switch (stage) {
1133 ufs_mtk_pwr_change_notify(struct ufs_hba *hba, enum ufs_notify_change_status stage, struct ufs_pa_layer_attr *dev_max_params, struct ufs_pa_layer_attr *dev_req_params) argument
1234 ufs_mtk_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status stage) argument
/linux-master/arch/x86/kvm/
H A Dkvm_emulate.h219 enum x86_intercept_stage stage);
/linux-master/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-qcom.c221 * be AARCH64 stage 1 but double check because the arm-smmu code assumes
225 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
/linux-master/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.c1582 * VMID 0 is reserved for stage-2 bypass EL1 STEs, see
2077 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
2168 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
2287 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
2325 /* Reserve VMID 0 for stage-2 bypass STEs */
2346 /* Restrict the stage to what we can actually support */
2348 smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
2350 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
2352 switch (smmu_domain->stage) {
2598 if (smmu_domain->stage
[all...]
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Ddm.c2418 static u8 stage; local
2431 if (cur_stage != stage) {
2436 } else if (cur_stage == 3 && (stage == 1 || stage == 2)) {
2441 stage = cur_stage;
/linux-master/fs/btrfs/
H A Dtree-log.c90 * stage (0) is to only pin down the blocks we find
91 * the second stage (1) is to make sure that all the inodes
94 * The last stage is to deal with directories and links and extents
282 * processing the log tree. The stage field tells us which part
297 /* what stage of the replay code we're currently in */
298 int stage; member in struct:walk_control
303 * the LOG_WALK_REPLAY_INODES stage.
2375 * gets called in two different stages. The first stage just looks
2378 * The second stage copies all the other item types from the log into
2379 * the subvolume. The two stage approac
[all...]
/linux-master/lib/zstd/compress/
H A Dzstd_compress.c628 RETURN_ERROR(stage_wrong, "can only set params in ctx init stage");
1000 "The context is in the wrong stage!");
1013 "Can't set pledgedSrcSize when not in init stage.");
1067 "Can't load a dictionary when ctx is not in init stage.");
1106 "Can't ref a dict when ctx not in init stage.");
1116 "Can't ref a pool when ctx not in init stage.");
1130 "Can't ref a prefix when ctx not in init stage.");
1152 "Can't reset parameters only when not in init stage.");
1746 * note : `params` are assumed fully validated at this stage.
1851 zc->stage
[all...]
/linux-master/arch/x86/kvm/svm/
H A Dsvm.c4409 .stage = X86_ICPT_PRE_EXCEPT, }
4411 .stage = X86_ICPT_POST_EXCEPT, }
4413 .stage = X86_ICPT_POST_MEMACCESS, }
4417 enum x86_intercept_stage stage; member in struct:__x86_intercept
4474 enum x86_intercept_stage stage,
4487 if (stage != icpt_info.stage)
4472 svm_check_intercept(struct kvm_vcpu *vcpu, struct x86_instruction_info *info, enum x86_intercept_stage stage, struct x86_exception *exception) argument
/linux-master/drivers/dma/sh/
H A Drcar-dmac.c422 * Program the descriptor stage interrupt to occur after the end
423 * of the first stage.
438 * descriptor stage interrupt in infinite repeat mode.
1495 unsigned int stage; local
1500 * cyclic descriptor when a descriptor stage end interrupt is
1506 /* Program the interrupt pointer to the next stage. */
1507 stage = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
1509 rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(stage));
/linux-master/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_dpia.c79 uint8_t stage; member in struct:dpia_set_config_data::__anon355
201 /* Convert DC training pattern to DPIA training stage. */

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