1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2009-2013 Realtek Corporation.*/ 3 4#include "../wifi.h" 5#include "../pci.h" 6#include "../ps.h" 7#include "reg.h" 8#include "def.h" 9#include "phy.h" 10#include "rf.h" 11#include "dm.h" 12#include "table.h" 13 14static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw, 15 enum radio_path rfpath, u32 offset); 16static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw, 17 enum radio_path rfpath, u32 offset, 18 u32 data); 19static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw); 20static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); 21static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 22 u8 configtype); 23static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw, 24 u8 configtype); 25static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw); 26static bool _rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 27 u32 cmdtableidx, u32 cmdtablesz, 28 enum swchnlcmd_id cmdid, u32 para1, 29 u32 para2, u32 msdelay); 30static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 31 u8 channel, u8 *stage, u8 *step, 32 u32 *delay); 33 34static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 35 enum wireless_mode wirelessmode, 36 u8 txpwridx); 37static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw); 38static void rtl88e_phy_set_io(struct ieee80211_hw *hw); 39 40u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 41{ 42 struct rtl_priv *rtlpriv = rtl_priv(hw); 43 u32 returnvalue, originalvalue, bitshift; 44 45 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 46 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); 47 originalvalue = rtl_read_dword(rtlpriv, regaddr); 48 bitshift = calculate_bit_shift(bitmask); 49 returnvalue = (originalvalue & bitmask) >> bitshift; 50 51 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 52 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, 53 regaddr, originalvalue); 54 55 return returnvalue; 56 57} 58 59void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw, 60 u32 regaddr, u32 bitmask, u32 data) 61{ 62 struct rtl_priv *rtlpriv = rtl_priv(hw); 63 u32 originalvalue, bitshift; 64 65 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 66 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 67 regaddr, bitmask, data); 68 69 if (bitmask != MASKDWORD) { 70 originalvalue = rtl_read_dword(rtlpriv, regaddr); 71 bitshift = calculate_bit_shift(bitmask); 72 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 73 } 74 75 rtl_write_dword(rtlpriv, regaddr, data); 76 77 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 78 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 79 regaddr, bitmask, data); 80} 81 82u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw, 83 enum radio_path rfpath, u32 regaddr, u32 bitmask) 84{ 85 struct rtl_priv *rtlpriv = rtl_priv(hw); 86 u32 original_value, readback_value, bitshift; 87 88 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 89 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 90 regaddr, rfpath, bitmask); 91 92 spin_lock(&rtlpriv->locks.rf_lock); 93 94 95 original_value = _rtl88e_phy_rf_serial_read(hw, rfpath, regaddr); 96 bitshift = calculate_bit_shift(bitmask); 97 readback_value = (original_value & bitmask) >> bitshift; 98 99 spin_unlock(&rtlpriv->locks.rf_lock); 100 101 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 102 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 103 regaddr, rfpath, bitmask, original_value); 104 return readback_value; 105} 106 107void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw, 108 enum radio_path rfpath, 109 u32 regaddr, u32 bitmask, u32 data) 110{ 111 struct rtl_priv *rtlpriv = rtl_priv(hw); 112 u32 original_value, bitshift; 113 114 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 115 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 116 regaddr, bitmask, data, rfpath); 117 118 spin_lock(&rtlpriv->locks.rf_lock); 119 120 if (bitmask != RFREG_OFFSET_MASK) { 121 original_value = _rtl88e_phy_rf_serial_read(hw, 122 rfpath, 123 regaddr); 124 bitshift = calculate_bit_shift(bitmask); 125 data = 126 ((original_value & (~bitmask)) | 127 (data << bitshift)); 128 } 129 130 _rtl88e_phy_rf_serial_write(hw, rfpath, regaddr, data); 131 132 133 spin_unlock(&rtlpriv->locks.rf_lock); 134 135 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 136 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 137 regaddr, bitmask, data, rfpath); 138} 139 140static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw, 141 enum radio_path rfpath, u32 offset) 142{ 143 struct rtl_priv *rtlpriv = rtl_priv(hw); 144 struct rtl_phy *rtlphy = &rtlpriv->phy; 145 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 146 u32 newoffset; 147 u32 tmplong, tmplong2; 148 u8 rfpi_enable = 0; 149 u32 retvalue; 150 151 offset &= 0xff; 152 newoffset = offset; 153 if (RT_CANNOT_IO(hw)) { 154 pr_err("return all one\n"); 155 return 0xFFFFFFFF; 156 } 157 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 158 if (rfpath == RF90_PATH_A) 159 tmplong2 = tmplong; 160 else 161 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 162 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 163 (newoffset << 23) | BLSSIREADEDGE; 164 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 165 tmplong & (~BLSSIREADEDGE)); 166 udelay(10); 167 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 168 udelay(120); 169 if (rfpath == RF90_PATH_A) 170 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 171 BIT(8)); 172 else if (rfpath == RF90_PATH_B) 173 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 174 BIT(8)); 175 if (rfpi_enable) 176 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 177 BLSSIREADBACKDATA); 178 else 179 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 180 BLSSIREADBACKDATA); 181 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 182 "RFR-%d Addr[0x%x]=0x%x\n", 183 rfpath, pphyreg->rf_rb, retvalue); 184 return retvalue; 185} 186 187static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw, 188 enum radio_path rfpath, u32 offset, 189 u32 data) 190{ 191 u32 data_and_addr; 192 u32 newoffset; 193 struct rtl_priv *rtlpriv = rtl_priv(hw); 194 struct rtl_phy *rtlphy = &rtlpriv->phy; 195 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 196 197 if (RT_CANNOT_IO(hw)) { 198 pr_err("stop\n"); 199 return; 200 } 201 offset &= 0xff; 202 newoffset = offset; 203 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 204 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 205 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 206 "RFW-%d Addr[0x%x]=0x%x\n", 207 rfpath, pphyreg->rf3wire_offset, data_and_addr); 208} 209 210bool rtl88e_phy_mac_config(struct ieee80211_hw *hw) 211{ 212 struct rtl_priv *rtlpriv = rtl_priv(hw); 213 bool rtstatus = _rtl88e_phy_config_mac_with_headerfile(hw); 214 215 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); 216 return rtstatus; 217} 218 219bool rtl88e_phy_bb_config(struct ieee80211_hw *hw) 220{ 221 bool rtstatus = true; 222 struct rtl_priv *rtlpriv = rtl_priv(hw); 223 u16 regval; 224 u8 b_reg_hwparafile = 1; 225 u32 tmp; 226 _rtl88e_phy_init_bb_rf_register_definition(hw); 227 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 228 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, 229 regval | BIT(13) | BIT(0) | BIT(1)); 230 231 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB); 232 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 233 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | 234 FEN_BB_GLB_RSTN | FEN_BBRSTB); 235 tmp = rtl_read_dword(rtlpriv, 0x4c); 236 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); 237 if (b_reg_hwparafile == 1) 238 rtstatus = _rtl88e_phy_bb8188e_config_parafile(hw); 239 return rtstatus; 240} 241 242bool rtl88e_phy_rf_config(struct ieee80211_hw *hw) 243{ 244 return rtl88e_phy_rf6052_config(hw); 245} 246 247static bool _rtl88e_check_condition(struct ieee80211_hw *hw, 248 const u32 condition) 249{ 250 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 251 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 252 u32 _board = rtlefuse->board_type; /*need efuse define*/ 253 u32 _interface = rtlhal->interface; 254 u32 _platform = 0x08;/*SupportPlatform */ 255 u32 cond; 256 257 if (condition == 0xCDCDCDCD) 258 return true; 259 260 cond = condition & 0xFF; 261 if ((_board & cond) == 0 && cond != 0x1F) 262 return false; 263 264 cond = condition & 0xFF00; 265 cond = cond >> 8; 266 if ((_interface & cond) == 0 && cond != 0x07) 267 return false; 268 269 cond = condition & 0xFF0000; 270 cond = cond >> 16; 271 if ((_platform & cond) == 0 && cond != 0x0F) 272 return false; 273 return true; 274} 275 276static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw, u32 addr, 277 u32 data, enum radio_path rfpath, 278 u32 regaddr) 279{ 280 if (addr == 0xffe) { 281 mdelay(50); 282 } else if (addr == 0xfd) { 283 mdelay(5); 284 } else if (addr == 0xfc) { 285 mdelay(1); 286 } else if (addr == 0xfb) { 287 udelay(50); 288 } else if (addr == 0xfa) { 289 udelay(5); 290 } else if (addr == 0xf9) { 291 udelay(1); 292 } else { 293 rtl_set_rfreg(hw, rfpath, regaddr, 294 RFREG_OFFSET_MASK, 295 data); 296 udelay(1); 297 } 298} 299 300static void _rtl8188e_config_rf_radio_a(struct ieee80211_hw *hw, 301 u32 addr, u32 data) 302{ 303 u32 content = 0x1000; /*RF Content: radio_a_txt*/ 304 u32 maskforphyset = (u32)(content & 0xE000); 305 306 _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A, 307 addr | maskforphyset); 308} 309 310static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw, 311 u32 addr, u32 data) 312{ 313 if (addr == 0xfe) { 314 mdelay(50); 315 } else if (addr == 0xfd) { 316 mdelay(5); 317 } else if (addr == 0xfc) { 318 mdelay(1); 319 } else if (addr == 0xfb) { 320 udelay(50); 321 } else if (addr == 0xfa) { 322 udelay(5); 323 } else if (addr == 0xf9) { 324 udelay(1); 325 } else { 326 rtl_set_bbreg(hw, addr, MASKDWORD, data); 327 udelay(1); 328 } 329} 330 331static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw) 332{ 333 struct rtl_priv *rtlpriv = rtl_priv(hw); 334 struct rtl_phy *rtlphy = &rtlpriv->phy; 335 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 336 bool rtstatus; 337 338 rtstatus = phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_PHY_REG); 339 if (!rtstatus) { 340 pr_err("Write BB Reg Fail!!\n"); 341 return false; 342 } 343 344 if (!rtlefuse->autoload_failflag) { 345 rtlphy->pwrgroup_cnt = 0; 346 rtstatus = 347 phy_config_bb_with_pghdr(hw, BASEBAND_CONFIG_PHY_REG); 348 } 349 if (!rtstatus) { 350 pr_err("BB_PG Reg Fail!!\n"); 351 return false; 352 } 353 rtstatus = 354 phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB); 355 if (!rtstatus) { 356 pr_err("AGC Table Fail\n"); 357 return false; 358 } 359 rtlphy->cck_high_power = 360 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200)); 361 362 return true; 363} 364 365static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) 366{ 367 struct rtl_priv *rtlpriv = rtl_priv(hw); 368 u32 i; 369 u32 arraylength; 370 u32 *ptrarray; 371 372 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8188EMACPHY_Array\n"); 373 arraylength = RTL8188EEMAC_1T_ARRAYLEN; 374 ptrarray = RTL8188EEMAC_1T_ARRAY; 375 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 376 "Img:RTL8188EEMAC_1T_ARRAY LEN %d\n", arraylength); 377 for (i = 0; i < arraylength; i = i + 2) 378 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]); 379 return true; 380} 381 382#define READ_NEXT_PAIR(v1, v2, i) \ 383 do { \ 384 i += 2; v1 = array_table[i]; \ 385 v2 = array_table[i+1]; \ 386 } while (0) 387 388static void handle_branch1(struct ieee80211_hw *hw, u16 arraylen, 389 u32 *array_table) 390{ 391 u32 v1; 392 u32 v2; 393 int i; 394 395 for (i = 0; i < arraylen; i = i + 2) { 396 v1 = array_table[i]; 397 v2 = array_table[i+1]; 398 if (v1 < 0xcdcdcdcd) { 399 _rtl8188e_config_bb_reg(hw, v1, v2); 400 } else { /*This line is the start line of branch.*/ 401 /* to protect READ_NEXT_PAIR not overrun */ 402 if (i >= arraylen - 2) 403 break; 404 405 if (!_rtl88e_check_condition(hw, array_table[i])) { 406 /*Discard the following (offset, data) pairs*/ 407 READ_NEXT_PAIR(v1, v2, i); 408 while (v2 != 0xDEAD && 409 v2 != 0xCDEF && 410 v2 != 0xCDCD && i < arraylen - 2) 411 READ_NEXT_PAIR(v1, v2, i); 412 i -= 2; /* prevent from for-loop += 2*/ 413 } else { /* Configure matched pairs and skip 414 * to end of if-else. 415 */ 416 READ_NEXT_PAIR(v1, v2, i); 417 while (v2 != 0xDEAD && 418 v2 != 0xCDEF && 419 v2 != 0xCDCD && i < arraylen - 2) { 420 _rtl8188e_config_bb_reg(hw, v1, v2); 421 READ_NEXT_PAIR(v1, v2, i); 422 } 423 424 while (v2 != 0xDEAD && i < arraylen - 2) 425 READ_NEXT_PAIR(v1, v2, i); 426 } 427 } 428 } 429} 430 431static void handle_branch2(struct ieee80211_hw *hw, u16 arraylen, 432 u32 *array_table) 433{ 434 struct rtl_priv *rtlpriv = rtl_priv(hw); 435 u32 v1; 436 u32 v2; 437 int i; 438 439 for (i = 0; i < arraylen; i = i + 2) { 440 v1 = array_table[i]; 441 v2 = array_table[i+1]; 442 if (v1 < 0xCDCDCDCD) { 443 rtl_set_bbreg(hw, array_table[i], MASKDWORD, 444 array_table[i + 1]); 445 udelay(1); 446 continue; 447 } else { /*This line is the start line of branch.*/ 448 /* to protect READ_NEXT_PAIR not overrun */ 449 if (i >= arraylen - 2) 450 break; 451 452 if (!_rtl88e_check_condition(hw, array_table[i])) { 453 /*Discard the following (offset, data) pairs*/ 454 READ_NEXT_PAIR(v1, v2, i); 455 while (v2 != 0xDEAD && 456 v2 != 0xCDEF && 457 v2 != 0xCDCD && i < arraylen - 2) 458 READ_NEXT_PAIR(v1, v2, i); 459 i -= 2; /* prevent from for-loop += 2*/ 460 } else { /* Configure matched pairs and skip 461 * to end of if-else. 462 */ 463 READ_NEXT_PAIR(v1, v2, i); 464 while (v2 != 0xDEAD && 465 v2 != 0xCDEF && 466 v2 != 0xCDCD && i < arraylen - 2) { 467 rtl_set_bbreg(hw, array_table[i], 468 MASKDWORD, 469 array_table[i + 1]); 470 udelay(1); 471 READ_NEXT_PAIR(v1, v2, i); 472 } 473 474 while (v2 != 0xDEAD && i < arraylen - 2) 475 READ_NEXT_PAIR(v1, v2, i); 476 } 477 } 478 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 479 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n", 480 array_table[i], array_table[i + 1]); 481 } 482} 483 484static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 485 u8 configtype) 486{ 487 u32 *array_table; 488 u16 arraylen; 489 490 if (configtype == BASEBAND_CONFIG_PHY_REG) { 491 arraylen = RTL8188EEPHY_REG_1TARRAYLEN; 492 array_table = RTL8188EEPHY_REG_1TARRAY; 493 handle_branch1(hw, arraylen, array_table); 494 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 495 arraylen = RTL8188EEAGCTAB_1TARRAYLEN; 496 array_table = RTL8188EEAGCTAB_1TARRAY; 497 handle_branch2(hw, arraylen, array_table); 498 } 499 return true; 500} 501 502static void store_pwrindex_rate_offset(struct ieee80211_hw *hw, 503 u32 regaddr, u32 bitmask, 504 u32 data) 505{ 506 struct rtl_priv *rtlpriv = rtl_priv(hw); 507 struct rtl_phy *rtlphy = &rtlpriv->phy; 508 int count = rtlphy->pwrgroup_cnt; 509 510 if (regaddr == RTXAGC_A_RATE18_06) { 511 rtlphy->mcs_txpwrlevel_origoffset[count][0] = data; 512 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 513 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", 514 count, 515 rtlphy->mcs_txpwrlevel_origoffset[count][0]); 516 } 517 if (regaddr == RTXAGC_A_RATE54_24) { 518 rtlphy->mcs_txpwrlevel_origoffset[count][1] = data; 519 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 520 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", 521 count, 522 rtlphy->mcs_txpwrlevel_origoffset[count][1]); 523 } 524 if (regaddr == RTXAGC_A_CCK1_MCS32) { 525 rtlphy->mcs_txpwrlevel_origoffset[count][6] = data; 526 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 527 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", 528 count, 529 rtlphy->mcs_txpwrlevel_origoffset[count][6]); 530 } 531 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) { 532 rtlphy->mcs_txpwrlevel_origoffset[count][7] = data; 533 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 534 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", 535 count, 536 rtlphy->mcs_txpwrlevel_origoffset[count][7]); 537 } 538 if (regaddr == RTXAGC_A_MCS03_MCS00) { 539 rtlphy->mcs_txpwrlevel_origoffset[count][2] = data; 540 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 541 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", 542 count, 543 rtlphy->mcs_txpwrlevel_origoffset[count][2]); 544 } 545 if (regaddr == RTXAGC_A_MCS07_MCS04) { 546 rtlphy->mcs_txpwrlevel_origoffset[count][3] = data; 547 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 548 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", 549 count, 550 rtlphy->mcs_txpwrlevel_origoffset[count][3]); 551 } 552 if (regaddr == RTXAGC_A_MCS11_MCS08) { 553 rtlphy->mcs_txpwrlevel_origoffset[count][4] = data; 554 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 555 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", 556 count, 557 rtlphy->mcs_txpwrlevel_origoffset[count][4]); 558 } 559 if (regaddr == RTXAGC_A_MCS15_MCS12) { 560 rtlphy->mcs_txpwrlevel_origoffset[count][5] = data; 561 if (get_rf_type(rtlphy) == RF_1T1R) { 562 count++; 563 rtlphy->pwrgroup_cnt = count; 564 } 565 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 566 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", 567 count, 568 rtlphy->mcs_txpwrlevel_origoffset[count][5]); 569 } 570 if (regaddr == RTXAGC_B_RATE18_06) { 571 rtlphy->mcs_txpwrlevel_origoffset[count][8] = data; 572 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 573 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", 574 count, 575 rtlphy->mcs_txpwrlevel_origoffset[count][8]); 576 } 577 if (regaddr == RTXAGC_B_RATE54_24) { 578 rtlphy->mcs_txpwrlevel_origoffset[count][9] = data; 579 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 580 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", 581 count, 582 rtlphy->mcs_txpwrlevel_origoffset[count][9]); 583 } 584 if (regaddr == RTXAGC_B_CCK1_55_MCS32) { 585 rtlphy->mcs_txpwrlevel_origoffset[count][14] = data; 586 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 587 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", 588 count, 589 rtlphy->mcs_txpwrlevel_origoffset[count][14]); 590 } 591 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) { 592 rtlphy->mcs_txpwrlevel_origoffset[count][15] = data; 593 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 594 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", 595 count, 596 rtlphy->mcs_txpwrlevel_origoffset[count][15]); 597 } 598 if (regaddr == RTXAGC_B_MCS03_MCS00) { 599 rtlphy->mcs_txpwrlevel_origoffset[count][10] = data; 600 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 601 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", 602 count, 603 rtlphy->mcs_txpwrlevel_origoffset[count][10]); 604 } 605 if (regaddr == RTXAGC_B_MCS07_MCS04) { 606 rtlphy->mcs_txpwrlevel_origoffset[count][11] = data; 607 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 608 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", 609 count, 610 rtlphy->mcs_txpwrlevel_origoffset[count][11]); 611 } 612 if (regaddr == RTXAGC_B_MCS11_MCS08) { 613 rtlphy->mcs_txpwrlevel_origoffset[count][12] = data; 614 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 615 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", 616 count, 617 rtlphy->mcs_txpwrlevel_origoffset[count][12]); 618 } 619 if (regaddr == RTXAGC_B_MCS15_MCS12) { 620 rtlphy->mcs_txpwrlevel_origoffset[count][13] = data; 621 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 622 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", 623 count, 624 rtlphy->mcs_txpwrlevel_origoffset[count][13]); 625 if (get_rf_type(rtlphy) != RF_1T1R) { 626 count++; 627 rtlphy->pwrgroup_cnt = count; 628 } 629 } 630} 631 632static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw, u8 configtype) 633{ 634 struct rtl_priv *rtlpriv = rtl_priv(hw); 635 int i; 636 u32 *phy_reg_page; 637 u16 phy_reg_page_len; 638 u32 v1 = 0, v2 = 0; 639 640 phy_reg_page_len = RTL8188EEPHY_REG_ARRAY_PGLEN; 641 phy_reg_page = RTL8188EEPHY_REG_ARRAY_PG; 642 643 if (configtype == BASEBAND_CONFIG_PHY_REG) { 644 for (i = 0; i < phy_reg_page_len; i = i + 3) { 645 v1 = phy_reg_page[i]; 646 v2 = phy_reg_page[i+1]; 647 648 if (v1 < 0xcdcdcdcd) { 649 if (phy_reg_page[i] == 0xfe) 650 mdelay(50); 651 else if (phy_reg_page[i] == 0xfd) 652 mdelay(5); 653 else if (phy_reg_page[i] == 0xfc) 654 mdelay(1); 655 else if (phy_reg_page[i] == 0xfb) 656 udelay(50); 657 else if (phy_reg_page[i] == 0xfa) 658 udelay(5); 659 else if (phy_reg_page[i] == 0xf9) 660 udelay(1); 661 662 store_pwrindex_rate_offset(hw, phy_reg_page[i], 663 phy_reg_page[i + 1], 664 phy_reg_page[i + 2]); 665 continue; 666 } else { 667 if (!_rtl88e_check_condition(hw, 668 phy_reg_page[i])) { 669 /*don't need the hw_body*/ 670 i += 2; /* skip the pair of expression*/ 671 /* to protect 'i+1' 'i+2' not overrun */ 672 if (i >= phy_reg_page_len - 2) 673 break; 674 675 v1 = phy_reg_page[i]; 676 v2 = phy_reg_page[i+1]; 677 while (v2 != 0xDEAD && 678 i < phy_reg_page_len - 5) { 679 i += 3; 680 v1 = phy_reg_page[i]; 681 v2 = phy_reg_page[i+1]; 682 } 683 } 684 } 685 } 686 } else { 687 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, 688 "configtype != BaseBand_Config_PHY_REG\n"); 689 } 690 return true; 691} 692 693#define READ_NEXT_RF_PAIR(v1, v2, i) \ 694do { \ 695 i += 2; \ 696 v1 = radioa_array_table[i]; \ 697 v2 = radioa_array_table[i+1]; \ 698} while (0) 699 700static void process_path_a(struct ieee80211_hw *hw, 701 u16 radioa_arraylen, 702 u32 *radioa_array_table) 703{ 704 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 705 u32 v1, v2; 706 int i; 707 708 for (i = 0; i < radioa_arraylen; i = i + 2) { 709 v1 = radioa_array_table[i]; 710 v2 = radioa_array_table[i+1]; 711 if (v1 < 0xcdcdcdcd) { 712 _rtl8188e_config_rf_radio_a(hw, v1, v2); 713 } else { /*This line is the start line of branch.*/ 714 /* to protect READ_NEXT_PAIR not overrun */ 715 if (i >= radioa_arraylen - 2) 716 break; 717 718 if (!_rtl88e_check_condition(hw, radioa_array_table[i])) { 719 /*Discard the following (offset, data) pairs*/ 720 READ_NEXT_RF_PAIR(v1, v2, i); 721 while (v2 != 0xDEAD && 722 v2 != 0xCDEF && 723 v2 != 0xCDCD && 724 i < radioa_arraylen - 2) { 725 READ_NEXT_RF_PAIR(v1, v2, i); 726 } 727 i -= 2; /* prevent from for-loop += 2*/ 728 } else { /* Configure matched pairs and 729 * skip to end of if-else. 730 */ 731 READ_NEXT_RF_PAIR(v1, v2, i); 732 while (v2 != 0xDEAD && 733 v2 != 0xCDEF && 734 v2 != 0xCDCD && 735 i < radioa_arraylen - 2) { 736 _rtl8188e_config_rf_radio_a(hw, v1, v2); 737 READ_NEXT_RF_PAIR(v1, v2, i); 738 } 739 740 while (v2 != 0xDEAD && 741 i < radioa_arraylen - 2) 742 READ_NEXT_RF_PAIR(v1, v2, i); 743 } 744 } 745 } 746 747 if (rtlhal->oem_id == RT_CID_819X_HP) 748 _rtl8188e_config_rf_radio_a(hw, 0x52, 0x7E4BD); 749} 750 751bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 752 enum radio_path rfpath) 753{ 754 struct rtl_priv *rtlpriv = rtl_priv(hw); 755 u32 *radioa_array_table; 756 u16 radioa_arraylen; 757 758 radioa_arraylen = RTL8188EE_RADIOA_1TARRAYLEN; 759 radioa_array_table = RTL8188EE_RADIOA_1TARRAY; 760 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 761 "Radio_A:RTL8188EE_RADIOA_1TARRAY %d\n", radioa_arraylen); 762 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 763 switch (rfpath) { 764 case RF90_PATH_A: 765 process_path_a(hw, radioa_arraylen, radioa_array_table); 766 break; 767 case RF90_PATH_B: 768 case RF90_PATH_C: 769 case RF90_PATH_D: 770 break; 771 } 772 return true; 773} 774 775void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 776{ 777 struct rtl_priv *rtlpriv = rtl_priv(hw); 778 struct rtl_phy *rtlphy = &rtlpriv->phy; 779 780 rtlphy->default_initialgain[0] = 781 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 782 rtlphy->default_initialgain[1] = 783 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 784 rtlphy->default_initialgain[2] = 785 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 786 rtlphy->default_initialgain[3] = 787 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 788 789 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 790 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 791 rtlphy->default_initialgain[0], 792 rtlphy->default_initialgain[1], 793 rtlphy->default_initialgain[2], 794 rtlphy->default_initialgain[3]); 795 796 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, 797 MASKBYTE0); 798 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 799 MASKDWORD); 800 801 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 802 "Default framesync (0x%x) = 0x%x\n", 803 ROFDM0_RXDETECTOR3, rtlphy->framesync); 804} 805 806static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 807{ 808 struct rtl_priv *rtlpriv = rtl_priv(hw); 809 struct rtl_phy *rtlphy = &rtlpriv->phy; 810 811 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 812 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 813 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 814 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 815 816 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; 817 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; 818 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 819 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 820 821 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 822 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 823 824 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 825 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 826 827 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 828 RFPGA0_XA_LSSIPARAMETER; 829 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 830 RFPGA0_XB_LSSIPARAMETER; 831 832 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; 833 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; 834 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; 835 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; 836 837 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 838 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 839 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 840 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 841 842 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 843 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 844 845 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 846 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 847 848 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = 849 RFPGA0_XAB_SWITCHCONTROL; 850 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = 851 RFPGA0_XAB_SWITCHCONTROL; 852 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = 853 RFPGA0_XCD_SWITCHCONTROL; 854 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = 855 RFPGA0_XCD_SWITCHCONTROL; 856 857 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; 858 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; 859 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 860 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 861 862 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; 863 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; 864 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 865 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 866 867 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; 868 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; 869 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE; 870 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; 871 872 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; 873 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; 874 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 875 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 876 877 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; 878 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; 879 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; 880 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; 881 882 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; 883 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; 884 885 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 886 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 887 888 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; 889 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; 890} 891 892void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) 893{ 894 struct rtl_priv *rtlpriv = rtl_priv(hw); 895 struct rtl_phy *rtlphy = &rtlpriv->phy; 896 u8 txpwr_level; 897 long txpwr_dbm; 898 899 txpwr_level = rtlphy->cur_cck_txpwridx; 900 txpwr_dbm = _rtl88e_phy_txpwr_idx_to_dbm(hw, 901 WIRELESS_MODE_B, txpwr_level); 902 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 903 if (_rtl88e_phy_txpwr_idx_to_dbm(hw, 904 WIRELESS_MODE_G, 905 txpwr_level) > txpwr_dbm) 906 txpwr_dbm = 907 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, 908 txpwr_level); 909 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 910 if (_rtl88e_phy_txpwr_idx_to_dbm(hw, 911 WIRELESS_MODE_N_24G, 912 txpwr_level) > txpwr_dbm) 913 txpwr_dbm = 914 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, 915 txpwr_level); 916 *powerlevel = txpwr_dbm; 917} 918 919static void handle_path_a(struct rtl_efuse *rtlefuse, u8 index, 920 u8 *cckpowerlevel, u8 *ofdmpowerlevel, 921 u8 *bw20powerlevel, u8 *bw40powerlevel) 922{ 923 cckpowerlevel[RF90_PATH_A] = 924 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; 925 /*-8~7 */ 926 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][index] > 0x0f) 927 bw20powerlevel[RF90_PATH_A] = 928 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] - 929 (~(rtlefuse->txpwr_ht20diff[RF90_PATH_A][index]) + 1); 930 else 931 bw20powerlevel[RF90_PATH_A] = 932 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] + 933 rtlefuse->txpwr_ht20diff[RF90_PATH_A][index]; 934 if (rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index] > 0xf) 935 ofdmpowerlevel[RF90_PATH_A] = 936 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] - 937 (~(rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index])+1); 938 else 939 ofdmpowerlevel[RF90_PATH_A] = 940 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] + 941 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index]; 942 bw40powerlevel[RF90_PATH_A] = 943 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; 944} 945 946static void _rtl88e_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 947 u8 *cckpowerlevel, u8 *ofdmpowerlevel, 948 u8 *bw20powerlevel, u8 *bw40powerlevel) 949{ 950 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 951 u8 index = (channel - 1); 952 u8 rf_path = 0; 953 954 for (rf_path = 0; rf_path < 2; rf_path++) { 955 if (rf_path == RF90_PATH_A) { 956 handle_path_a(rtlefuse, index, cckpowerlevel, 957 ofdmpowerlevel, bw20powerlevel, 958 bw40powerlevel); 959 } else if (rf_path == RF90_PATH_B) { 960 cckpowerlevel[RF90_PATH_B] = 961 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; 962 bw20powerlevel[RF90_PATH_B] = 963 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] + 964 rtlefuse->txpwr_ht20diff[RF90_PATH_B][index]; 965 ofdmpowerlevel[RF90_PATH_B] = 966 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] + 967 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][index]; 968 bw40powerlevel[RF90_PATH_B] = 969 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; 970 } 971 } 972 973} 974 975static void _rtl88e_ccxpower_index_check(struct ieee80211_hw *hw, 976 u8 channel, u8 *cckpowerlevel, 977 u8 *ofdmpowerlevel, u8 *bw20powerlevel, 978 u8 *bw40powerlevel) 979{ 980 struct rtl_priv *rtlpriv = rtl_priv(hw); 981 struct rtl_phy *rtlphy = &rtlpriv->phy; 982 983 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 984 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 985 rtlphy->cur_bw20_txpwridx = bw20powerlevel[0]; 986 rtlphy->cur_bw40_txpwridx = bw40powerlevel[0]; 987 988} 989 990void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 991{ 992 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 993 u8 cckpowerlevel[MAX_TX_COUNT] = {0}; 994 u8 ofdmpowerlevel[MAX_TX_COUNT] = {0}; 995 u8 bw20powerlevel[MAX_TX_COUNT] = {0}; 996 u8 bw40powerlevel[MAX_TX_COUNT] = {0}; 997 998 if (!rtlefuse->txpwr_fromeprom) 999 return; 1000 _rtl88e_get_txpower_index(hw, channel, 1001 &cckpowerlevel[0], &ofdmpowerlevel[0], 1002 &bw20powerlevel[0], &bw40powerlevel[0]); 1003 _rtl88e_ccxpower_index_check(hw, channel, 1004 &cckpowerlevel[0], &ofdmpowerlevel[0], 1005 &bw20powerlevel[0], &bw40powerlevel[0]); 1006 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); 1007 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], 1008 &bw20powerlevel[0], 1009 &bw40powerlevel[0], channel); 1010} 1011 1012static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 1013 enum wireless_mode wirelessmode, 1014 u8 txpwridx) 1015{ 1016 long offset; 1017 long pwrout_dbm; 1018 1019 switch (wirelessmode) { 1020 case WIRELESS_MODE_B: 1021 offset = -7; 1022 break; 1023 case WIRELESS_MODE_G: 1024 case WIRELESS_MODE_N_24G: 1025 offset = -8; 1026 break; 1027 default: 1028 offset = -8; 1029 break; 1030 } 1031 pwrout_dbm = txpwridx / 2 + offset; 1032 return pwrout_dbm; 1033} 1034 1035void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) 1036{ 1037 struct rtl_priv *rtlpriv = rtl_priv(hw); 1038 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1039 enum io_type iotype; 1040 1041 if (!is_hal_stop(rtlhal)) { 1042 switch (operation) { 1043 case SCAN_OPT_BACKUP_BAND0: 1044 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN; 1045 rtlpriv->cfg->ops->set_hw_reg(hw, 1046 HW_VAR_IO_CMD, 1047 (u8 *)&iotype); 1048 1049 break; 1050 case SCAN_OPT_RESTORE: 1051 iotype = IO_CMD_RESUME_DM_BY_SCAN; 1052 rtlpriv->cfg->ops->set_hw_reg(hw, 1053 HW_VAR_IO_CMD, 1054 (u8 *)&iotype); 1055 break; 1056 default: 1057 pr_err("Unknown Scan Backup operation.\n"); 1058 break; 1059 } 1060 } 1061} 1062 1063void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw) 1064{ 1065 struct rtl_priv *rtlpriv = rtl_priv(hw); 1066 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1067 struct rtl_phy *rtlphy = &rtlpriv->phy; 1068 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1069 u8 reg_bw_opmode; 1070 u8 reg_prsr_rsc; 1071 1072 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 1073 "Switch to %s bandwidth\n", 1074 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 1075 "20MHz" : "40MHz"); 1076 1077 if (is_hal_stop(rtlhal)) { 1078 rtlphy->set_bwmode_inprogress = false; 1079 return; 1080 } 1081 1082 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 1083 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 1084 1085 switch (rtlphy->current_chan_bw) { 1086 case HT_CHANNEL_WIDTH_20: 1087 reg_bw_opmode |= BW_OPMODE_20MHZ; 1088 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 1089 break; 1090 case HT_CHANNEL_WIDTH_20_40: 1091 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 1092 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 1093 reg_prsr_rsc = 1094 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5); 1095 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 1096 break; 1097 default: 1098 pr_err("unknown bandwidth: %#X\n", 1099 rtlphy->current_chan_bw); 1100 break; 1101 } 1102 1103 switch (rtlphy->current_chan_bw) { 1104 case HT_CHANNEL_WIDTH_20: 1105 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 1106 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 1107 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/ 1108 break; 1109 case HT_CHANNEL_WIDTH_20_40: 1110 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 1111 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 1112 1113 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 1114 (mac->cur_40_prime_sc >> 1)); 1115 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 1116 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/ 1117 1118 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 1119 (mac->cur_40_prime_sc == 1120 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 1121 break; 1122 default: 1123 pr_err("unknown bandwidth: %#X\n", 1124 rtlphy->current_chan_bw); 1125 break; 1126 } 1127 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 1128 rtlphy->set_bwmode_inprogress = false; 1129 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "\n"); 1130} 1131 1132void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw, 1133 enum nl80211_channel_type ch_type) 1134{ 1135 struct rtl_priv *rtlpriv = rtl_priv(hw); 1136 struct rtl_phy *rtlphy = &rtlpriv->phy; 1137 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1138 u8 tmp_bw = rtlphy->current_chan_bw; 1139 1140 if (rtlphy->set_bwmode_inprogress) 1141 return; 1142 rtlphy->set_bwmode_inprogress = true; 1143 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 1144 rtl88e_phy_set_bw_mode_callback(hw); 1145 } else { 1146 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1147 "false driver sleep or unload\n"); 1148 rtlphy->set_bwmode_inprogress = false; 1149 rtlphy->current_chan_bw = tmp_bw; 1150 } 1151} 1152 1153void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw) 1154{ 1155 struct rtl_priv *rtlpriv = rtl_priv(hw); 1156 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1157 struct rtl_phy *rtlphy = &rtlpriv->phy; 1158 u32 delay; 1159 1160 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 1161 "switch to channel%d\n", rtlphy->current_channel); 1162 if (is_hal_stop(rtlhal)) 1163 return; 1164 do { 1165 if (!rtlphy->sw_chnl_inprogress) 1166 break; 1167 if (!_rtl88e_phy_sw_chnl_step_by_step 1168 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, 1169 &rtlphy->sw_chnl_step, &delay)) { 1170 if (delay > 0) 1171 mdelay(delay); 1172 else 1173 continue; 1174 } else { 1175 rtlphy->sw_chnl_inprogress = false; 1176 } 1177 break; 1178 } while (true); 1179 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n"); 1180} 1181 1182u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw) 1183{ 1184 struct rtl_priv *rtlpriv = rtl_priv(hw); 1185 struct rtl_phy *rtlphy = &rtlpriv->phy; 1186 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1187 1188 if (rtlphy->sw_chnl_inprogress) 1189 return 0; 1190 if (rtlphy->set_bwmode_inprogress) 1191 return 0; 1192 WARN_ONCE((rtlphy->current_channel > 14), 1193 "rtl8188ee: WIRELESS_MODE_G but channel>14"); 1194 rtlphy->sw_chnl_inprogress = true; 1195 rtlphy->sw_chnl_stage = 0; 1196 rtlphy->sw_chnl_step = 0; 1197 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 1198 rtl88e_phy_sw_chnl_callback(hw); 1199 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD, 1200 "sw_chnl_inprogress false schedule workitem current channel %d\n", 1201 rtlphy->current_channel); 1202 rtlphy->sw_chnl_inprogress = false; 1203 } else { 1204 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD, 1205 "sw_chnl_inprogress false driver sleep or unload\n"); 1206 rtlphy->sw_chnl_inprogress = false; 1207 } 1208 return 1; 1209} 1210 1211static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 1212 u8 channel, u8 *stage, u8 *step, 1213 u32 *delay) 1214{ 1215 struct rtl_priv *rtlpriv = rtl_priv(hw); 1216 struct rtl_phy *rtlphy = &rtlpriv->phy; 1217 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 1218 u32 precommoncmdcnt; 1219 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 1220 u32 postcommoncmdcnt; 1221 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 1222 u32 rfdependcmdcnt; 1223 struct swchnlcmd *currentcmd = NULL; 1224 u8 rfpath; 1225 u8 num_total_rfpath = rtlphy->num_total_rfpath; 1226 1227 precommoncmdcnt = 0; 1228 _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 1229 MAX_PRECMD_CNT, 1230 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 1231 _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 1232 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 1233 1234 postcommoncmdcnt = 0; 1235 1236 _rtl88e_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 1237 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 1238 1239 rfdependcmdcnt = 0; 1240 1241 WARN_ONCE((channel < 1 || channel > 14), 1242 "rtl8188ee: illegal channel for Zebra: %d\n", channel); 1243 1244 _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 1245 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 1246 RF_CHNLBW, channel, 10); 1247 1248 _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 1249 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 1250 0); 1251 1252 do { 1253 switch (*stage) { 1254 case 0: 1255 currentcmd = &precommoncmd[*step]; 1256 break; 1257 case 1: 1258 currentcmd = &rfdependcmd[*step]; 1259 break; 1260 case 2: 1261 currentcmd = &postcommoncmd[*step]; 1262 break; 1263 default: 1264 pr_err("Invalid 'stage' = %d, Check it!\n", 1265 *stage); 1266 return true; 1267 } 1268 1269 if (currentcmd->cmdid == CMDID_END) { 1270 if ((*stage) == 2) 1271 return true; 1272 (*stage)++; 1273 (*step) = 0; 1274 continue; 1275 } 1276 1277 switch (currentcmd->cmdid) { 1278 case CMDID_SET_TXPOWEROWER_LEVEL: 1279 rtl88e_phy_set_txpower_level(hw, channel); 1280 break; 1281 case CMDID_WRITEPORT_ULONG: 1282 rtl_write_dword(rtlpriv, currentcmd->para1, 1283 currentcmd->para2); 1284 break; 1285 case CMDID_WRITEPORT_USHORT: 1286 rtl_write_word(rtlpriv, currentcmd->para1, 1287 (u16)currentcmd->para2); 1288 break; 1289 case CMDID_WRITEPORT_UCHAR: 1290 rtl_write_byte(rtlpriv, currentcmd->para1, 1291 (u8)currentcmd->para2); 1292 break; 1293 case CMDID_RF_WRITEREG: 1294 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 1295 rtlphy->rfreg_chnlval[rfpath] = 1296 ((rtlphy->rfreg_chnlval[rfpath] & 1297 0xfffffc00) | currentcmd->para2); 1298 1299 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1300 currentcmd->para1, 1301 RFREG_OFFSET_MASK, 1302 rtlphy->rfreg_chnlval[rfpath]); 1303 } 1304 break; 1305 default: 1306 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 1307 "switch case %#x not processed\n", 1308 currentcmd->cmdid); 1309 break; 1310 } 1311 1312 break; 1313 } while (true); 1314 1315 (*delay) = currentcmd->msdelay; 1316 (*step)++; 1317 return false; 1318} 1319 1320static bool _rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 1321 u32 cmdtableidx, u32 cmdtablesz, 1322 enum swchnlcmd_id cmdid, 1323 u32 para1, u32 para2, u32 msdelay) 1324{ 1325 struct swchnlcmd *pcmd; 1326 1327 if (cmdtable == NULL) { 1328 WARN_ONCE(true, "rtl8188ee: cmdtable cannot be NULL.\n"); 1329 return false; 1330 } 1331 1332 if (cmdtableidx >= cmdtablesz) 1333 return false; 1334 1335 pcmd = cmdtable + cmdtableidx; 1336 pcmd->cmdid = cmdid; 1337 pcmd->para1 = para1; 1338 pcmd->para2 = para2; 1339 pcmd->msdelay = msdelay; 1340 return true; 1341} 1342 1343static u8 _rtl88e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) 1344{ 1345 u32 reg_eac, reg_e94, reg_e9c; 1346 u8 result = 0x00; 1347 1348 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c); 1349 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c); 1350 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a); 1351 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000); 1352 1353 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1354 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1355 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1356 1357 mdelay(IQK_DELAY_TIME); 1358 1359 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1360 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1361 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1362 rtl_get_bbreg(hw, 0xea4, MASKDWORD); 1363 1364 if (!(reg_eac & BIT(28)) && 1365 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && 1366 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) 1367 result |= 0x01; 1368 return result; 1369} 1370 1371static u8 _rtl88e_phy_path_b_iqk(struct ieee80211_hw *hw) 1372{ 1373 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1374 u8 result = 0x00; 1375 1376 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); 1377 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); 1378 mdelay(IQK_DELAY_TIME); 1379 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1380 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1381 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1382 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1383 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1384 1385 if (!(reg_eac & BIT(31)) && 1386 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && 1387 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) 1388 result |= 0x01; 1389 else 1390 return result; 1391 if (!(reg_eac & BIT(30)) && 1392 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && 1393 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) 1394 result |= 0x02; 1395 return result; 1396} 1397 1398static u8 _rtl88e_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb) 1399{ 1400 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32temp; 1401 u8 result = 0x00; 1402 1403 /*Get TXIMR Setting*/ 1404 /*Modify RX IQK mode table*/ 1405 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 1406 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); 1407 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); 1408 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); 1409 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); 1410 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 1411 1412 /*IQK Setting*/ 1413 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); 1414 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800); 1415 1416 /*path a IQK setting*/ 1417 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c); 1418 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c); 1419 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804); 1420 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); 1421 1422 /*LO calibration Setting*/ 1423 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); 1424 /*one shot,path A LOK & iqk*/ 1425 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); 1426 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 1427 1428 mdelay(IQK_DELAY_TIME); 1429 1430 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 1431 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); 1432 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); 1433 1434 1435 if (!(reg_eac & BIT(28)) && 1436 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && 1437 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) 1438 result |= 0x01; 1439 else 1440 return result; 1441 1442 u32temp = 0x80007C00 | (reg_e94&0x3FF0000) | 1443 ((reg_e9c&0x3FF0000) >> 16); 1444 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); 1445 /*RX IQK*/ 1446 /*Modify RX IQK mode table*/ 1447 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 1448 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); 1449 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); 1450 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); 1451 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); 1452 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 1453 1454 /*IQK Setting*/ 1455 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 1456 1457 /*path a IQK setting*/ 1458 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c); 1459 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c); 1460 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05); 1461 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05); 1462 1463 /*LO calibration Setting*/ 1464 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); 1465 /*one shot,path A LOK & iqk*/ 1466 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); 1467 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 1468 1469 mdelay(IQK_DELAY_TIME); 1470 1471 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 1472 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); 1473 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); 1474 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); 1475 1476 if (!(reg_eac & BIT(27)) && 1477 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && 1478 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) 1479 result |= 0x02; 1480 return result; 1481} 1482 1483static void _rtl88e_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, 1484 bool iqk_ok, long result[][8], 1485 u8 final_candidate, bool btxonly) 1486{ 1487 u32 oldval_0, x, tx0_a, reg; 1488 long y, tx0_c; 1489 1490 if (final_candidate == 0xFF) { 1491 return; 1492 } else if (iqk_ok) { 1493 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 1494 MASKDWORD) >> 22) & 0x3FF; 1495 x = result[final_candidate][0]; 1496 if ((x & 0x00000200) != 0) 1497 x = x | 0xFFFFFC00; 1498 tx0_a = (x * oldval_0) >> 8; 1499 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); 1500 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), 1501 ((x * oldval_0 >> 7) & 0x1)); 1502 y = result[final_candidate][1]; 1503 if ((y & 0x00000200) != 0) 1504 y = y | 0xFFFFFC00; 1505 tx0_c = (y * oldval_0) >> 8; 1506 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 1507 ((tx0_c & 0x3C0) >> 6)); 1508 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, 1509 (tx0_c & 0x3F)); 1510 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), 1511 ((y * oldval_0 >> 7) & 0x1)); 1512 if (btxonly) 1513 return; 1514 reg = result[final_candidate][2]; 1515 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); 1516 reg = result[final_candidate][3] & 0x3F; 1517 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); 1518 reg = (result[final_candidate][3] >> 6) & 0xF; 1519 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); 1520 } 1521} 1522 1523static void _rtl88e_phy_save_adda_registers(struct ieee80211_hw *hw, 1524 u32 *addareg, u32 *addabackup, 1525 u32 registernum) 1526{ 1527 u32 i; 1528 1529 for (i = 0; i < registernum; i++) 1530 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); 1531} 1532 1533static void _rtl88e_phy_save_mac_registers(struct ieee80211_hw *hw, 1534 u32 *macreg, u32 *macbackup) 1535{ 1536 struct rtl_priv *rtlpriv = rtl_priv(hw); 1537 u32 i; 1538 1539 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1540 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); 1541 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); 1542} 1543 1544static void _rtl88e_phy_reload_adda_registers(struct ieee80211_hw *hw, 1545 u32 *addareg, u32 *addabackup, 1546 u32 regiesternum) 1547{ 1548 u32 i; 1549 1550 for (i = 0; i < regiesternum; i++) 1551 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); 1552} 1553 1554static void _rtl88e_phy_reload_mac_registers(struct ieee80211_hw *hw, 1555 u32 *macreg, u32 *macbackup) 1556{ 1557 struct rtl_priv *rtlpriv = rtl_priv(hw); 1558 u32 i; 1559 1560 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1561 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); 1562 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]); 1563} 1564 1565static void _rtl88e_phy_path_adda_on(struct ieee80211_hw *hw, 1566 u32 *addareg, bool is_patha_on, bool is2t) 1567{ 1568 u32 pathon; 1569 u32 i; 1570 1571 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4; 1572 if (!is2t) { 1573 pathon = 0x0bdb25a0; 1574 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); 1575 } else { 1576 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); 1577 } 1578 1579 for (i = 1; i < IQK_ADDA_REG_NUM; i++) 1580 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); 1581} 1582 1583static void _rtl88e_phy_mac_setting_calibration(struct ieee80211_hw *hw, 1584 u32 *macreg, u32 *macbackup) 1585{ 1586 struct rtl_priv *rtlpriv = rtl_priv(hw); 1587 u32 i = 0; 1588 1589 rtl_write_byte(rtlpriv, macreg[i], 0x3F); 1590 1591 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) 1592 rtl_write_byte(rtlpriv, macreg[i], 1593 (u8) (macbackup[i] & (~BIT(3)))); 1594 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); 1595} 1596 1597static void _rtl88e_phy_path_a_standby(struct ieee80211_hw *hw) 1598{ 1599 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); 1600 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); 1601 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1602} 1603 1604static void _rtl88e_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode) 1605{ 1606 u32 mode; 1607 1608 mode = pi_mode ? 0x01000100 : 0x01000000; 1609 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); 1610 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); 1611} 1612 1613static bool _rtl88e_phy_simularity_compare(struct ieee80211_hw *hw, 1614 long result[][8], u8 c1, u8 c2) 1615{ 1616 u32 i, j, diff, simularity_bitmap, bound; 1617 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1618 1619 u8 final_candidate[2] = { 0xFF, 0xFF }; 1620 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version); 1621 1622 if (is2t) 1623 bound = 8; 1624 else 1625 bound = 4; 1626 1627 simularity_bitmap = 0; 1628 1629 for (i = 0; i < bound; i++) { 1630 diff = (result[c1][i] > result[c2][i]) ? 1631 (result[c1][i] - result[c2][i]) : 1632 (result[c2][i] - result[c1][i]); 1633 1634 if (diff > MAX_TOLERANCE) { 1635 if ((i == 2 || i == 6) && !simularity_bitmap) { 1636 if (result[c1][i] + result[c1][i + 1] == 0) 1637 final_candidate[(i / 4)] = c2; 1638 else if (result[c2][i] + result[c2][i + 1] == 0) 1639 final_candidate[(i / 4)] = c1; 1640 else 1641 simularity_bitmap = simularity_bitmap | 1642 (1 << i); 1643 } else 1644 simularity_bitmap = 1645 simularity_bitmap | (1 << i); 1646 } 1647 } 1648 1649 if (simularity_bitmap == 0) { 1650 for (i = 0; i < (bound / 4); i++) { 1651 if (final_candidate[i] != 0xFF) { 1652 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 1653 result[3][j] = 1654 result[final_candidate[i]][j]; 1655 bresult = false; 1656 } 1657 } 1658 return bresult; 1659 } else if (!(simularity_bitmap & 0x0F)) { 1660 for (i = 0; i < 4; i++) 1661 result[3][i] = result[c1][i]; 1662 return false; 1663 } else if (!(simularity_bitmap & 0xF0) && is2t) { 1664 for (i = 4; i < 8; i++) 1665 result[3][i] = result[c1][i]; 1666 return false; 1667 } else { 1668 return false; 1669 } 1670 1671} 1672 1673static void _rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, 1674 long result[][8], u8 t, bool is2t) 1675{ 1676 struct rtl_priv *rtlpriv = rtl_priv(hw); 1677 struct rtl_phy *rtlphy = &rtlpriv->phy; 1678 u32 i; 1679 u8 patha_ok, pathb_ok; 1680 u32 adda_reg[IQK_ADDA_REG_NUM] = { 1681 0x85c, 0xe6c, 0xe70, 0xe74, 1682 0xe78, 0xe7c, 0xe80, 0xe84, 1683 0xe88, 0xe8c, 0xed0, 0xed4, 1684 0xed8, 0xedc, 0xee0, 0xeec 1685 }; 1686 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1687 0x522, 0x550, 0x551, 0x040 1688 }; 1689 u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1690 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR, 1691 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c, 1692 0x870, 0x860, 0x864, 0x800 1693 }; 1694 const u32 retrycount = 2; 1695 1696 if (t == 0) { 1697 _rtl88e_phy_save_adda_registers(hw, adda_reg, 1698 rtlphy->adda_backup, 16); 1699 _rtl88e_phy_save_mac_registers(hw, iqk_mac_reg, 1700 rtlphy->iqk_mac_backup); 1701 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg, 1702 rtlphy->iqk_bb_backup, 1703 IQK_BB_REG_NUM); 1704 } 1705 _rtl88e_phy_path_adda_on(hw, adda_reg, true, is2t); 1706 if (t == 0) { 1707 rtlphy->rfpi_enable = 1708 (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 1709 } 1710 1711 if (!rtlphy->rfpi_enable) 1712 _rtl88e_phy_pi_mode_switch(hw, true); 1713 /*BB Setting*/ 1714 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00); 1715 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); 1716 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); 1717 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); 1718 1719 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01); 1720 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01); 1721 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00); 1722 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00); 1723 1724 if (is2t) { 1725 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); 1726 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); 1727 } 1728 _rtl88e_phy_mac_setting_calibration(hw, iqk_mac_reg, 1729 rtlphy->iqk_mac_backup); 1730 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 1731 if (is2t) 1732 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 1733 1734 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1735 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); 1736 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800); 1737 for (i = 0; i < retrycount; i++) { 1738 patha_ok = _rtl88e_phy_path_a_iqk(hw, is2t); 1739 if (patha_ok == 0x01) { 1740 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1741 "Path A Tx IQK Success!!\n"); 1742 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1743 0x3FF0000) >> 16; 1744 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1745 0x3FF0000) >> 16; 1746 break; 1747 } 1748 } 1749 1750 for (i = 0; i < retrycount; i++) { 1751 patha_ok = _rtl88e_phy_path_a_rx_iqk(hw, is2t); 1752 if (patha_ok == 0x03) { 1753 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1754 "Path A Rx IQK Success!!\n"); 1755 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 1756 0x3FF0000) >> 16; 1757 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 1758 0x3FF0000) >> 16; 1759 break; 1760 } else { 1761 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1762 "Path a RX iqk fail!!!\n"); 1763 } 1764 } 1765 1766 if (0 == patha_ok) 1767 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1768 "Path A IQK Success!!\n"); 1769 if (is2t) { 1770 _rtl88e_phy_path_a_standby(hw); 1771 _rtl88e_phy_path_adda_on(hw, adda_reg, false, is2t); 1772 for (i = 0; i < retrycount; i++) { 1773 pathb_ok = _rtl88e_phy_path_b_iqk(hw); 1774 if (pathb_ok == 0x03) { 1775 result[t][4] = (rtl_get_bbreg(hw, 1776 0xeb4, 1777 MASKDWORD) & 1778 0x3FF0000) >> 16; 1779 result[t][5] = 1780 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1781 0x3FF0000) >> 16; 1782 result[t][6] = 1783 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & 1784 0x3FF0000) >> 16; 1785 result[t][7] = 1786 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & 1787 0x3FF0000) >> 16; 1788 break; 1789 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1790 result[t][4] = (rtl_get_bbreg(hw, 1791 0xeb4, 1792 MASKDWORD) & 1793 0x3FF0000) >> 16; 1794 } 1795 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1796 0x3FF0000) >> 16; 1797 } 1798 } 1799 1800 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 1801 1802 if (t != 0) { 1803 if (!rtlphy->rfpi_enable) 1804 _rtl88e_phy_pi_mode_switch(hw, false); 1805 _rtl88e_phy_reload_adda_registers(hw, adda_reg, 1806 rtlphy->adda_backup, 16); 1807 _rtl88e_phy_reload_mac_registers(hw, iqk_mac_reg, 1808 rtlphy->iqk_mac_backup); 1809 _rtl88e_phy_reload_adda_registers(hw, iqk_bb_reg, 1810 rtlphy->iqk_bb_backup, 1811 IQK_BB_REG_NUM); 1812 1813 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); 1814 if (is2t) 1815 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); 1816 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); 1817 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); 1818 } 1819 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "88ee IQK Finish!!\n"); 1820} 1821 1822static void _rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 1823{ 1824 u8 tmpreg; 1825 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; 1826 struct rtl_priv *rtlpriv = rtl_priv(hw); 1827 1828 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 1829 1830 if ((tmpreg & 0x70) != 0) 1831 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 1832 else 1833 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1834 1835 if ((tmpreg & 0x70) != 0) { 1836 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); 1837 1838 if (is2t) 1839 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, 1840 MASK12BITS); 1841 1842 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, 1843 (rf_a_mode & 0x8FFFF) | 0x10000); 1844 1845 if (is2t) 1846 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, 1847 (rf_b_mode & 0x8FFFF) | 0x10000); 1848 } 1849 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); 1850 1851 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); 1852 1853 mdelay(100); 1854 1855 if ((tmpreg & 0x70) != 0) { 1856 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 1857 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); 1858 1859 if (is2t) 1860 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, 1861 rf_b_mode); 1862 } else { 1863 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1864 } 1865 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1866} 1867 1868static void _rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, 1869 bool bmain, bool is2t) 1870{ 1871 struct rtl_priv *rtlpriv = rtl_priv(hw); 1872 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1873 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1874 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1875 1876 if (is_hal_stop(rtlhal)) { 1877 u8 u1btmp; 1878 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0); 1879 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7)); 1880 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); 1881 } 1882 if (is2t) { 1883 if (bmain) 1884 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1885 BIT(5) | BIT(6), 0x1); 1886 else 1887 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1888 BIT(5) | BIT(6), 0x2); 1889 } else { 1890 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); 1891 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); 1892 1893 /* We use the RF definition of MAIN and AUX, 1894 * left antenna and right antenna repectively. 1895 * Default output at AUX. 1896 */ 1897 if (bmain) { 1898 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 1899 BIT(14) | BIT(13) | BIT(12), 0); 1900 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1901 BIT(5) | BIT(4) | BIT(3), 0); 1902 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 1903 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); 1904 } else { 1905 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 1906 BIT(14) | BIT(13) | BIT(12), 1); 1907 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1908 BIT(5) | BIT(4) | BIT(3), 1); 1909 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 1910 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); 1911 } 1912 } 1913} 1914 1915#undef IQK_ADDA_REG_NUM 1916#undef IQK_DELAY_TIME 1917 1918void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) 1919{ 1920 struct rtl_priv *rtlpriv = rtl_priv(hw); 1921 struct rtl_phy *rtlphy = &rtlpriv->phy; 1922 long result[4][8]; 1923 u8 i, final_candidate; 1924 bool b_patha_ok; 1925 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, 1926 reg_tmp = 0; 1927 bool is12simular, is13simular, is23simular; 1928 u32 iqk_bb_reg[9] = { 1929 ROFDM0_XARXIQIMBALANCE, 1930 ROFDM0_XBRXIQIMBALANCE, 1931 ROFDM0_ECCATHRESHOLD, 1932 ROFDM0_AGCRSSITABLE, 1933 ROFDM0_XATXIQIMBALANCE, 1934 ROFDM0_XBTXIQIMBALANCE, 1935 ROFDM0_XCTXAFE, 1936 ROFDM0_XDTXAFE, 1937 ROFDM0_RXIQEXTANTA 1938 }; 1939 1940 if (b_recovery) { 1941 _rtl88e_phy_reload_adda_registers(hw, 1942 iqk_bb_reg, 1943 rtlphy->iqk_bb_backup, 9); 1944 return; 1945 } 1946 1947 for (i = 0; i < 8; i++) { 1948 result[0][i] = 0; 1949 result[1][i] = 0; 1950 result[2][i] = 0; 1951 result[3][i] = 0; 1952 } 1953 final_candidate = 0xff; 1954 b_patha_ok = false; 1955 is12simular = false; 1956 is23simular = false; 1957 is13simular = false; 1958 for (i = 0; i < 3; i++) { 1959 if (get_rf_type(rtlphy) == RF_2T2R) 1960 _rtl88e_phy_iq_calibrate(hw, result, i, true); 1961 else 1962 _rtl88e_phy_iq_calibrate(hw, result, i, false); 1963 if (i == 1) { 1964 is12simular = 1965 _rtl88e_phy_simularity_compare(hw, result, 0, 1); 1966 if (is12simular) { 1967 final_candidate = 0; 1968 break; 1969 } 1970 } 1971 if (i == 2) { 1972 is13simular = 1973 _rtl88e_phy_simularity_compare(hw, result, 0, 2); 1974 if (is13simular) { 1975 final_candidate = 0; 1976 break; 1977 } 1978 is23simular = 1979 _rtl88e_phy_simularity_compare(hw, result, 1, 2); 1980 if (is23simular) { 1981 final_candidate = 1; 1982 } else { 1983 for (i = 0; i < 8; i++) 1984 reg_tmp += result[3][i]; 1985 1986 if (reg_tmp != 0) 1987 final_candidate = 3; 1988 else 1989 final_candidate = 0xFF; 1990 } 1991 } 1992 } 1993 for (i = 0; i < 4; i++) { 1994 reg_e94 = result[i][0]; 1995 reg_e9c = result[i][1]; 1996 reg_ea4 = result[i][2]; 1997 reg_eb4 = result[i][4]; 1998 reg_ebc = result[i][5]; 1999 } 2000 if (final_candidate != 0xff) { 2001 reg_e94 = result[final_candidate][0]; 2002 reg_e9c = result[final_candidate][1]; 2003 reg_ea4 = result[final_candidate][2]; 2004 reg_eb4 = result[final_candidate][4]; 2005 reg_ebc = result[final_candidate][5]; 2006 rtlphy->reg_eb4 = reg_eb4; 2007 rtlphy->reg_ebc = reg_ebc; 2008 rtlphy->reg_e94 = reg_e94; 2009 rtlphy->reg_e9c = reg_e9c; 2010 b_patha_ok = true; 2011 } else { 2012 rtlphy->reg_e94 = 0x100; 2013 rtlphy->reg_eb4 = 0x100; 2014 rtlphy->reg_e9c = 0x0; 2015 rtlphy->reg_ebc = 0x0; 2016 } 2017 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ 2018 _rtl88e_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, 2019 final_candidate, 2020 (reg_ea4 == 0)); 2021 if (final_candidate != 0xFF) { 2022 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) 2023 rtlphy->iqk_matrix[0].value[0][i] = 2024 result[final_candidate][i]; 2025 rtlphy->iqk_matrix[0].iqk_done = true; 2026 2027 } 2028 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg, 2029 rtlphy->iqk_bb_backup, 9); 2030} 2031 2032void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw) 2033{ 2034 struct rtl_priv *rtlpriv = rtl_priv(hw); 2035 struct rtl_phy *rtlphy = &rtlpriv->phy; 2036 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 2037 u32 timeout = 2000, timecount = 0; 2038 2039 while (rtlpriv->mac80211.act_scanning && timecount < timeout) { 2040 udelay(50); 2041 timecount += 50; 2042 } 2043 2044 rtlphy->lck_inprogress = true; 2045 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2046 "LCK:Start!!! currentband %x delay %d ms\n", 2047 rtlhal->current_bandtype, timecount); 2048 2049 _rtl88e_phy_lc_calibrate(hw, false); 2050 2051 rtlphy->lck_inprogress = false; 2052} 2053 2054void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) 2055{ 2056 _rtl88e_phy_set_rfpath_switch(hw, bmain, false); 2057} 2058 2059bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 2060{ 2061 struct rtl_priv *rtlpriv = rtl_priv(hw); 2062 struct rtl_phy *rtlphy = &rtlpriv->phy; 2063 bool postprocessing = false; 2064 2065 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 2066 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 2067 iotype, rtlphy->set_io_inprogress); 2068 do { 2069 switch (iotype) { 2070 case IO_CMD_RESUME_DM_BY_SCAN: 2071 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 2072 "[IO CMD] Resume DM after scan.\n"); 2073 postprocessing = true; 2074 break; 2075 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 2076 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 2077 "[IO CMD] Pause DM before scan.\n"); 2078 postprocessing = true; 2079 break; 2080 default: 2081 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 2082 "switch case %#x not processed\n", iotype); 2083 break; 2084 } 2085 } while (false); 2086 if (postprocessing && !rtlphy->set_io_inprogress) { 2087 rtlphy->set_io_inprogress = true; 2088 rtlphy->current_io_type = iotype; 2089 } else { 2090 return false; 2091 } 2092 rtl88e_phy_set_io(hw); 2093 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype); 2094 return true; 2095} 2096 2097static void rtl88e_phy_set_io(struct ieee80211_hw *hw) 2098{ 2099 struct rtl_priv *rtlpriv = rtl_priv(hw); 2100 struct rtl_phy *rtlphy = &rtlpriv->phy; 2101 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 2102 2103 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 2104 "--->Cmd(%#x), set_io_inprogress(%d)\n", 2105 rtlphy->current_io_type, rtlphy->set_io_inprogress); 2106 switch (rtlphy->current_io_type) { 2107 case IO_CMD_RESUME_DM_BY_SCAN: 2108 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; 2109 /*rtl92c_dm_write_dig(hw);*/ 2110 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel); 2111 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83); 2112 break; 2113 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 2114 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue; 2115 dm_digtable->cur_igvalue = 0x17; 2116 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40); 2117 break; 2118 default: 2119 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 2120 "switch case %#x not processed\n", 2121 rtlphy->current_io_type); 2122 break; 2123 } 2124 rtlphy->set_io_inprogress = false; 2125 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 2126 "(%#x)\n", rtlphy->current_io_type); 2127} 2128 2129static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw) 2130{ 2131 struct rtl_priv *rtlpriv = rtl_priv(hw); 2132 2133 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 2134 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2135 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/ 2136 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2137 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2138 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2139} 2140 2141static void _rtl88ee_phy_set_rf_sleep(struct ieee80211_hw *hw) 2142{ 2143 struct rtl_priv *rtlpriv = rtl_priv(hw); 2144 2145 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 2146 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 2147 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2148 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 2149} 2150 2151static bool _rtl88ee_phy_set_rf_power_state(struct ieee80211_hw *hw, 2152 enum rf_pwrstate rfpwr_state) 2153{ 2154 struct rtl_priv *rtlpriv = rtl_priv(hw); 2155 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2156 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2157 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2158 bool bresult = true; 2159 u8 i, queue_id; 2160 struct rtl8192_tx_ring *ring = NULL; 2161 2162 switch (rfpwr_state) { 2163 case ERFON: 2164 if ((ppsc->rfpwr_state == ERFOFF) && 2165 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 2166 bool rtstatus; 2167 u32 initializecount = 0; 2168 2169 do { 2170 initializecount++; 2171 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2172 "IPS Set eRf nic enable\n"); 2173 rtstatus = rtl_ps_enable_nic(hw); 2174 } while (!rtstatus && 2175 (initializecount < 10)); 2176 RT_CLEAR_PS_LEVEL(ppsc, 2177 RT_RF_OFF_LEVL_HALT_NIC); 2178 } else { 2179 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2180 "Set ERFON slept:%d ms\n", 2181 jiffies_to_msecs(jiffies - 2182 ppsc->last_sleep_jiffies)); 2183 ppsc->last_awake_jiffies = jiffies; 2184 rtl88ee_phy_set_rf_on(hw); 2185 } 2186 if (mac->link_state == MAC80211_LINKED) { 2187 rtlpriv->cfg->ops->led_control(hw, 2188 LED_CTL_LINK); 2189 } else { 2190 rtlpriv->cfg->ops->led_control(hw, 2191 LED_CTL_NO_LINK); 2192 } 2193 break; 2194 case ERFOFF: 2195 for (queue_id = 0, i = 0; 2196 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 2197 ring = &pcipriv->dev.tx_ring[queue_id]; 2198 if (queue_id == BEACON_QUEUE || 2199 skb_queue_len(&ring->queue) == 0) { 2200 queue_id++; 2201 continue; 2202 } else { 2203 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 2204 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 2205 (i + 1), queue_id, 2206 skb_queue_len(&ring->queue)); 2207 2208 udelay(10); 2209 i++; 2210 } 2211 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 2212 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 2213 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 2214 MAX_DOZE_WAITING_TIMES_9x, 2215 queue_id, 2216 skb_queue_len(&ring->queue)); 2217 break; 2218 } 2219 } 2220 2221 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 2222 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2223 "IPS Set eRf nic disable\n"); 2224 rtl_ps_disable_nic(hw); 2225 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2226 } else { 2227 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) { 2228 rtlpriv->cfg->ops->led_control(hw, 2229 LED_CTL_NO_LINK); 2230 } else { 2231 rtlpriv->cfg->ops->led_control(hw, 2232 LED_CTL_POWER_OFF); 2233 } 2234 } 2235 break; 2236 case ERFSLEEP:{ 2237 if (ppsc->rfpwr_state == ERFOFF) 2238 break; 2239 for (queue_id = 0, i = 0; 2240 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 2241 ring = &pcipriv->dev.tx_ring[queue_id]; 2242 if (skb_queue_len(&ring->queue) == 0) { 2243 queue_id++; 2244 continue; 2245 } else { 2246 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 2247 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 2248 (i + 1), queue_id, 2249 skb_queue_len(&ring->queue)); 2250 2251 udelay(10); 2252 i++; 2253 } 2254 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 2255 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 2256 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 2257 MAX_DOZE_WAITING_TIMES_9x, 2258 queue_id, 2259 skb_queue_len(&ring->queue)); 2260 break; 2261 } 2262 } 2263 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 2264 "Set ERFSLEEP awaked:%d ms\n", 2265 jiffies_to_msecs(jiffies - 2266 ppsc->last_awake_jiffies)); 2267 ppsc->last_sleep_jiffies = jiffies; 2268 _rtl88ee_phy_set_rf_sleep(hw); 2269 break; 2270 } 2271 default: 2272 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 2273 "switch case %#x not processed\n", rfpwr_state); 2274 bresult = false; 2275 break; 2276 } 2277 if (bresult) 2278 ppsc->rfpwr_state = rfpwr_state; 2279 return bresult; 2280} 2281 2282bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw, 2283 enum rf_pwrstate rfpwr_state) 2284{ 2285 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2286 2287 bool bresult = false; 2288 2289 if (rfpwr_state == ppsc->rfpwr_state) 2290 return bresult; 2291 bresult = _rtl88ee_phy_set_rf_power_state(hw, rfpwr_state); 2292 return bresult; 2293} 2294