/linux-master/drivers/net/ethernet/sfc/siena/ |
H A D | siena.c | 114 tests->registers =
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H A D | ethtool_common.c | 324 efx_fill_test(n++, strings, data, &tests->registers, 325 "core", 0, "registers", NULL);
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/linux-master/drivers/gpu/drm/amd/amdkfd/ |
H A D | cwsr_trap_handler_gfx9.asm | 401 /* save HW registers */ 856 /* restore HW registers */
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H A D | cwsr_trap_handler_gfx10.asm | 520 /* save HW registers */ 1156 /* restore HW registers */
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/linux-master/drivers/firewire/ |
H A D | ohci.c | 182 __iomem char *registers; member in struct:fw_ohci 286 // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register, 579 writel(data, ohci->registers + offset); 584 return readl(ohci->registers + offset); 2087 * config_rom registers. Writing the header quadlet 2337 * most of the registers. In fact, on some cards (ALI M5251), 2338 * accessing registers in the SClk domain without LPS enabled 2433 * the ConfigRomHeader and BusOptions registers on bus reset. 2515 * ConfigRomHeader and BusOptions registers from the specified 2522 * controller will load be32 values in to these registers [all...] |
/linux-master/drivers/net/wireless/ath/ath10k/ |
H A D | core.h | 668 __le32 registers[REG_DUMP_COUNT_QCA988X]; member in struct:ath10k_fw_crash_data
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/linux-master/arch/m68k/fpsp040/ |
H A D | bindec.S | 110 | The registers are used as follows: 912 | Clean up and restore all registers used.
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/linux-master/sound/soc/codecs/ |
H A D | arizona-jack.c | 25 #include <linux/mfd/arizona/registers.h>
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H A D | wm8998.c | 27 #include <linux/mfd/arizona/registers.h>
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H A D | cs47l24.c | 27 #include <linux/mfd/arizona/registers.h>
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H A D | cs47l35.c | 25 #include <linux/mfd/madera/registers.h>
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H A D | cs47l15.c | 25 #include <linux/mfd/madera/registers.h> 33 /* Mid-mode registers */
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/linux-master/drivers/net/wireless/ath/ath5k/ |
H A D | debug.c | 78 /* debugfs: registers */ 87 /* just a few random registers, might want to add more */ 171 DEFINE_SEQ_ATTRIBUTE(registers); variable 987 debugfs_create_file("registers", 0400, phydir, ah, ®isters_fops);
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/linux-master/drivers/mfd/ |
H A D | wm8997-tables.c | 13 #include <linux/mfd/arizona/registers.h>
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H A D | wm8998-tables.c | 13 #include <linux/mfd/arizona/registers.h>
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H A D | cs47l35-tables.c | 13 #include <linux/mfd/madera/registers.h>
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H A D | cs47l24-tables.c | 13 #include <linux/mfd/arizona/registers.h>
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/linux-master/drivers/net/ethernet/sfc/ |
H A D | ethtool_common.c | 373 efx_fill_test(n++, strings, data, &tests->registers, 374 "core", 0, "registers", NULL);
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/linux-master/drivers/net/ethernet/sfc/falcon/ |
H A D | ethtool.c | 325 ef4_fill_test(n++, strings, data, &tests->registers, 326 "core", 0, "registers", NULL);
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/linux-master/drivers/scsi/smartpqi/ |
H A D | smartpqi.h | 60 * controller registers 64 * Some registers (those named sis_*) are only used when in 66 * PQI mode. There are a number of other SIS mode registers, 67 * but we don't use them, so only the SIS registers that we 91 * The PQI spec states that the PQI registers should be at 94 * with the SIS registers. So we map them at offset 4000h. 1301 struct pqi_ctrl_registers __iomem *registers; member in struct:pqi_ctrl_info
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/linux-master/drivers/power/supply/ |
H A D | bq2415x_charger.c | 42 /* reset state for all registers */ 509 /* reset all chip registers to default state */ 1444 static DEVICE_ATTR(registers, S_IWUSR | S_IRUGO,
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu.h | 1412 const u32 *registers,
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H A D | amdgpu_device.c | 1353 * amdgpu_device_program_register_sequence - program an array of registers. 1356 * @registers: pointer to the register array 1359 * Programs an array or registers with and or masks. 1360 * This is a helper for setting golden registers. 1363 const u32 *registers, 1373 reg = registers[i + 0]; 1374 and_mask = registers[i + 1]; 1375 or_mask = registers[i + 2]; 4455 /* Unmap all mapped bars - Doorbell, registers and VRAM */ 6234 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers 1362 amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 *registers, const u32 array_size) argument [all...] |
/linux-master/arch/x86/crypto/ |
H A D | aesni-intel_asm.S | 170 # states of %xmm registers %xmm6:%xmm15 not saved 171 # all %xmm registers are clobbered 186 # clobbers r12, and tmp xmm registers. 773 * %r10, %r11, %r12, %rax, %xmm5, %xmm6, %xmm7, %xmm8, %xmm9 registers 2523 * setup registers used by _aesni_inc
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/linux-master/arch/m68k/ifpsp060/src/ |
H A D | pfpsp.S | 2405 # (3) The "fmovm.l" instruction w/ 2 or 3 control registers. # 2973 # the instruction is a fmovm.l with 2 or 3 registers. 4231 # string of FP registers affected. This value is used as an index into # 4576 # easily changed if they were inputs passed in registers. 5249 # fmovm_ctrl(): emulate fmovm.l of control registers instr # 5266 # in order to see how many control registers to fetch from memory. # 6333 # only. All registers except d0 are kept intact. d0 becomes an 6356 movm.l &0x3000, -(%sp) # make some temp registers {d2/d3} 6414 movm.l (%sp)+, &0xc # restore scratch registers {d2/d3} 13549 # The registers ar [all...] |