Searched refs:reg_val (Results 176 - 200 of 396) sorted by relevance

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/linux-master/drivers/mmc/host/
H A Dsdhci-pci-o2micro.c323 u32 reg_val; local
350 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
351 reg_val &= ~SDHCI_CLOCK_CARD_EN;
352 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
362 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
363 reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
364 reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
365 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
374 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
375 reg_val |
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/linux-master/sound/soc/codecs/
H A Drt5616.c1015 unsigned int reg_val = 0; local
1022 reg_val |= RT5616_I2S_MS_S;
1033 reg_val |= RT5616_I2S_BP_INV;
1043 reg_val |= RT5616_I2S_DF_LEFT;
1046 reg_val |= RT5616_I2S_DF_PCM_A;
1049 reg_val |= RT5616_I2S_DF_PCM_B;
1057 RT5616_I2S_DF_MASK, reg_val);
1067 unsigned int reg_val = 0; local
1074 reg_val |= RT5616_SCLK_SRC_MCLK;
1077 reg_val |
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H A Drt1015.c753 unsigned int reg_val = 0, reg_val2 = 0; local
757 reg_val |= RT1015_TCON_TDM_MS_M;
760 reg_val |= RT1015_TCON_TDM_MS_S;
781 reg_val |= RT1015_I2S_M_DF_LEFT;
785 reg_val |= RT1015_I2S_M_DF_PCM_A;
789 reg_val |= RT1015_I2S_M_DF_PCM_B;
798 reg_val);
809 unsigned int reg_val = 0; local
816 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
820 reg_val |
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H A Drt715-sdca.c111 static inline unsigned int rt715_sdca_get_gain(unsigned int reg_val, argument
116 if (reg_val & BIT(15)) {
117 reg_val = ~(reg_val - 1) & 0xffff;
120 reg_val *= 1000;
121 reg_val >>= 8;
123 reg_val = gain_sft - reg_val / RT715_SDCA_DB_STEP;
125 reg_val = gain_sft + reg_val / RT715_SDCA_DB_STE
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H A Dtas2562.c475 u32 reg_val; local
477 reg_val = float_vol_db_lookup[ucontrol->value.integer.value[0]/2];
479 (reg_val & 0xff));
483 ((reg_val >> 8) & 0xff));
487 ((reg_val >> 16) & 0xff));
491 ((reg_val >> 24) & 0xff));
/linux-master/drivers/net/ethernet/intel/igb/
H A De1000_i210.c829 u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; local
836 reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO;
837 wr32(E1000_MDICNFG, reg_val);
866 reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16);
867 wr32(E1000_EEARBC_I210, reg_val);
875 reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16);
876 wr32(E1000_EEARBC_I210, reg_val);
/linux-master/sound/soc/sunxi/
H A Dsun4i-spdif.c268 u32 reg_val; local
351 reg_val = 0;
352 reg_val |= SUN4I_SPDIF_TXCFG_ASS;
353 reg_val |= fmt; /* set non audio and bit depth */
354 reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE;
355 reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1);
356 regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val);
/linux-master/drivers/thermal/
H A Drcar_gen3_thermal.c352 u32 reg_val; local
354 reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR);
355 reg_val &= ~THCTR_PONM;
356 rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val);
366 reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR);
367 reg_val |= THCTR_THSST;
368 rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val);
/linux-master/drivers/net/ethernet/hisilicon/hns3/hns3_common/
H A Dhclge_comm_cmd.c11 u32 reg_val; local
18 reg_val = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
19 reg_val &= HCLGE_COMM_NIC_SW_RST_RDY;
20 reg_val |= ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S;
21 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);
29 reg_val = ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S;
30 hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_DEPTH_REG, reg_val);
/linux-master/drivers/leds/
H A Dleds-lp50xx.c307 u8 led_offset, reg_val; local
313 reg_val = led_chip->bank_brt_reg;
315 reg_val = led_chip->led_brightness0_reg +
318 ret = regmap_write(led->priv->regmap, reg_val, brightness);
327 reg_val = led_chip->bank_mix_reg + i;
330 reg_val = led_chip->mix_out0_reg + led_offset;
333 ret = regmap_write(led->priv->regmap, reg_val,
/linux-master/drivers/scsi/hisi_sas/
H A Dhisi_sas_v3_hw.c877 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); local
883 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
888 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
889 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
2161 u32 reg_val; local
2163 reg_val = hisi_sas_read32(hisi_hba,
2166 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2168 AM_CTRL_GLOBAL, reg_val);
2175 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); local
2176 u32 dev_id = reg_val
2691 u32 status, reg_val; local
3175 u32 reg_val; local
3195 u32 reg_val; local
3224 u32 reg_val, mode_tmp; local
4333 u32 reg_val; local
4999 u32 reg_val; local
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/linux-master/drivers/gpio/
H A Dgpio-pca953x.c562 u32 reg_val; local
566 ret = regmap_read(chip->regmap, inreg, &reg_val);
570 return !!(reg_val & bit);
589 u32 reg_val; local
593 ret = regmap_read(chip->regmap, dirreg, &reg_val);
597 if (reg_val & bit)
607 DECLARE_BITMAP(reg_val, MAX_LINE);
611 ret = pca953x_read_regs(chip, chip->regs->input, reg_val);
615 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio);
623 DECLARE_BITMAP(reg_val, MAX_LIN
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.c1074 const uint16_t *reg_val)
1076 if (reg_val) {
1078 GAMUT_REMAP_C11, reg_val[0],
1079 GAMUT_REMAP_C12, reg_val[1]);
1081 GAMUT_REMAP_C13, reg_val[2],
1082 GAMUT_REMAP_C14, reg_val[3]);
1084 GAMUT_REMAP_C21, reg_val[4],
1085 GAMUT_REMAP_C22, reg_val[5]);
1087 GAMUT_REMAP_C23, reg_val[6],
1088 GAMUT_REMAP_C24, reg_val[
1072 program_gamut_remap( struct dce_transform *xfm_dce, const uint16_t *reg_val) argument
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/linux-master/drivers/hwmon/
H A Dltc4282.c1200 u32 reg_val, ilm_adjust; local
1203 ret = regmap_read(st->map, LTC4282_ADC_CTRL, &reg_val);
1207 st->energy_en = !FIELD_GET(LTC4282_METER_HALT_MASK, reg_val);
1209 ret = regmap_read(st->map, LTC4282_CTRL_MSB, &reg_val);
1213 *vin_mode = FIELD_GET(LTC4282_CTRL_VIN_MODE_MASK, reg_val);
1215 ret = regmap_read(st->map, LTC4282_ILIM_ADJUST, &reg_val);
1219 ilm_adjust = FIELD_GET(LTC4282_ILIM_ADJUST_MASK, reg_val);
1419 int reg_val; local
1423 reg_val = 0;
1426 reg_val
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H A Dchipcap2.c323 u16 reg_val; local
326 ret = cc2_read_reg(data, reg, &reg_val);
328 *val = cc2_rh_convert(reg_val);
421 u16 reg_val; local
424 ret = cc2_read_reg(data, reg, &reg_val);
428 *hyst = cc2_rh_convert(reg_val);
/linux-master/drivers/net/ethernet/intel/i40e/
H A Di40e_common.c546 u32 reg_val; local
553 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
554 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
555 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
558 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
560 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
562 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
2610 * @reg_val: register value
2616 u32 reg_addr, u64 *reg_val,
2624 if (reg_val
2615 i40e_aq_debug_read_register(struct i40e_hw *hw, u32 reg_addr, u64 *reg_val, struct i40e_asq_cmd_details *cmd_details) argument
2650 i40e_aq_debug_write_register(struct i40e_hw *hw, u32 reg_addr, u64 reg_val, struct i40e_asq_cmd_details *cmd_details) argument
4660 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); local
4745 i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, u32 *reg_val) argument
4779 i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, u32 reg_val) argument
4822 u16 reg_val; local
4918 i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, u32 reg_addr, u32 *reg_val, struct i40e_asq_cmd_details *cmd_details) argument
4984 i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, u32 reg_addr, u32 reg_val, struct i40e_asq_cmd_details *cmd_details) argument
5009 i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) argument
5075 i40e_aq_set_phy_register_ext(struct i40e_hw *hw, u8 phy_select, u8 dev_addr, bool page_change, bool set_mdio, u8 mdio_num, u32 reg_addr, u32 reg_val, struct i40e_asq_cmd_details *cmd_details) argument
5120 i40e_aq_get_phy_register_ext(struct i40e_hw *hw, u8 phy_select, u8 dev_addr, bool page_change, bool set_mdio, u8 mdio_num, u32 reg_addr, u32 *reg_val, struct i40e_asq_cmd_details *cmd_details) argument
[all...]
/linux-master/drivers/regulator/
H A Dhi6421-regulator.c388 unsigned int reg_val; local
391 regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val);
392 if (reg_val & info->mode_mask)
401 unsigned int reg_val; local
404 regmap_read(rdev->regmap, rdev->desc->enable_reg, &reg_val);
405 if (reg_val & info->mode_mask)
H A Dda9052-regulator.c115 int reg_val = 0; local
127 reg_val = i;
142 reg_val << 2);
147 reg_val << 6);
H A Dmax8660.c80 u8 reg_val = (max8660->shadow_regs[reg] & mask) | val; local
83 max8660_addresses[reg], reg_val);
86 max8660_addresses[reg], reg_val);
88 max8660->shadow_regs[reg] = reg_val;
/linux-master/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-params.c523 u32 reg_val = 0; local
538 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10);
540 reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
542 reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
543 rkisp1_write(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10, reg_val);
563 u32 reg_val = 0; local
578 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12);
580 reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
582 reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
583 reg_val
600 u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V10); local
630 u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP_V12); local
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/linux-master/drivers/net/phy/
H A Dnxp-tja11xx.c291 u16 reg_mask, reg_val; local
306 reg_val = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
314 reg_val |= (ret & 0xffff);
315 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
325 reg_val = ret & 0xffff;
326 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
/linux-master/arch/sparc/include/asm/
H A Dhypervisor.h3446 unsigned long *reg_val);
3448 unsigned long reg_val);
3456 unsigned long *reg_val);
3458 unsigned long reg_val);
3467 unsigned long *reg_val);
3469 unsigned long reg_val);
/linux-master/drivers/gpu/drm/xe/
H A Dxe_mmio.c465 u32 old, reg_val; local
468 reg_val = (old & ~clr) | set;
469 xe_mmio_write32(gt, reg, reg_val);
477 u32 reg_val; local
480 reg_val = xe_mmio_read32(gt, reg);
482 return (reg_val & mask) != eval ? -EINVAL : 0;
/linux-master/drivers/acpi/pmic/
H A Dintel_pmic_bxtwc.c300 unsigned int val, adc_val, reg_val; local
315 reg_val = temp_l | WHISKEY_COVE_ADC_HIGH_BIT(temp_h);
318 adc_val = reg_val * rlsb / 1000;
/linux-master/sound/soc/amd/acp/
H A Dacp-platform.c140 u32 pte_reg, pte_size, reg_val; local
148 reg_val = rsrc->sram_pte_offset;
149 writel(reg_val | BIT(31), adata->acp_base + pte_reg);

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