Searched refs:readl (Results 76 - 100 of 2405) sorted by relevance

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/linux-master/drivers/platform/x86/intel/pmt/
H A Dcrashlog.c67 u32 control = readl(entry->disc_table + CONTROL_OFFSET);
75 u32 control = readl(entry->disc_table + CONTROL_OFFSET);
83 u32 discovery_header = readl(entry->disc_table + CONTROL_OFFSET);
99 u32 control = readl(entry->disc_table + CONTROL_OFFSET);
114 u32 control = readl(entry->disc_table + CONTROL_OFFSET);
124 u32 control = readl(entry->disc_table + CONTROL_OFFSET);
239 header->access_type = GET_ACCESS(readl(disc_table));
240 header->guid = readl(disc_table + GUID_OFFSET);
241 header->base_offset = readl(disc_table + BASE_OFFSET);
244 header->size = GET_SIZE(readl(disc_tabl
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/linux-master/drivers/i3c/master/mipi-i3c-hci/
H A Dext_caps.c26 hci->vendor_mipi_id = readl(base + 0x04);
27 hci->vendor_version_id = readl(base + 0x08);
28 hci->vendor_product_id = readl(base + 0x0c);
47 u32 master_config = readl(base + 0x04);
61 u32 bus_instance = readl(base + 0x04);
70 u32 header = readl(base);
78 u32 mode_entry = readl(base);
90 u32 header = readl(base);
99 rate_entry = readl(base);
118 u32 autocmd_ext_caps = readl(bas
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/linux-master/drivers/mailbox/
H A Dsun6i-msgbox.c73 status = readl(mbox->regs + LOCAL_IRQ_EN_REG) &
74 readl(mbox->regs + LOCAL_IRQ_STAT_REG);
86 uint32_t msg = readl(mbox->regs + MSG_DATA_REG(n));
106 if (WARN_ON_ONCE(!(readl(mbox->regs + CTRL_REG(n)) & CTRL_TX(n))))
121 if (readl(mbox->regs + CTRL_REG(n)) & CTRL_RX(n)) {
124 readl(mbox->regs + MSG_DATA_REG(n));
129 writel(readl(mbox->regs + LOCAL_IRQ_EN_REG) | RX_IRQ(n),
144 if (readl(mbox->regs + CTRL_REG(n)) & CTRL_RX(n)) {
147 writel(readl(mbox->regs + LOCAL_IRQ_EN_REG) & ~RX_IRQ(n),
154 readl(mbo
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/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac4_core.c27 u32 value = readl(ioaddr + GMAC_CONFIG);
62 if ((GMAC_HW_FEAT_FPESEL & readl(ioaddr + GMAC_HW_FEATURE3)) >> 26)
83 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
102 ctrl2 = readl(ioaddr + GMAC_RXQ_CTRL2);
103 ctrl3 = readl(ioaddr + GMAC_RXQ_CTRL3);
146 value = readl(ioaddr + base_register);
169 value = readl(ioaddr + GMAC_RXQ_CTRL1);
192 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
213 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
242 u32 value = readl(ioadd
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H A Ddwmac5.c83 value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS);
131 value = readl(ioaddr + MTL_ECC_INT_STATUS);
179 value = readl(ioaddr + DMA_ECC_INT_STATUS);
209 value = readl(ioaddr + MTL_ECC_CONTROL);
224 value = readl(ioaddr + MTL_ECC_INT_ENABLE);
232 value = readl(ioaddr + DMA_ECC_INT_ENABLE);
241 value = readl(ioaddr + MAC_FSM_CONTROL);
249 value = readl(ioaddr + MTL_DPP_CONTROL);
278 mtl = readl(ioaddr + MTL_SAFETY_INT_STATUS);
279 dma = readl(ioadd
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H A Ddwxgmac2_core.c21 tx = readl(ioaddr + XGMAC_TX_CONFIG);
22 rx = readl(ioaddr + XGMAC_RX_CONFIG);
52 u32 tx = readl(ioaddr + XGMAC_TX_CONFIG);
53 u32 rx = readl(ioaddr + XGMAC_RX_CONFIG);
72 value = readl(ioaddr + XGMAC_RX_CONFIG);
79 return !!(readl(ioaddr + XGMAC_RX_CONFIG) & XGMAC_CONFIG_IPC);
88 value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue);
104 ctrl2 = readl(ioaddr + XGMAC_RXQ_CTRL2);
105 ctrl3 = readl(ioaddr + XGMAC_RXQ_CTRL3);
147 value = readl(ioadd
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/linux-master/drivers/clk/
H A Dclk-highbank.c48 reg = readl(hbclk->reg);
52 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
54 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
65 reg = readl(hbclk->reg);
75 reg = readl(hbclk->reg);
87 reg = readl(hbclk->reg);
98 reg = readl(hbclk->reg);
153 reg = readl(hbclk->reg);
165 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
167 while ((readl(hbcl
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H A Dclk-en7523.c179 val = readl(base + desc->base_reg);
198 val = readl(base + reg);
212 return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1);
222 val = readl(np_base + REG_PCI_CONTROL);
233 val = readl(np_base + REG_RESET_CONTROL1);
245 val = readl(np_base + REG_PCI_CONTROL);
260 val = readl(np_base + REG_PCI_CONTROL);
298 val = readl(cg->base + REG_PCI_CONTROL);
310 val = readl(np_base + REG_RESET_CONTROL1);
312 val = readl(np_bas
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/linux-master/drivers/usb/early/
H A Dehci-dbgp.c82 dbgp_printk(" Debug control: %08x", readl(&ehci_debug->control));
83 dbgp_printk(" ehci cmd : %08x", readl(&ehci_regs->command));
85 readl(&ehci_regs->configured_flag));
86 dbgp_printk(" ehci status : %08x", readl(&ehci_regs->status));
88 readl(&ehci_regs->port_status[dbgp_phys_port - 1]));
203 pids = readl(&ehci_debug->pids);
257 lo = readl(&ehci_debug->data03);
258 hi = readl(&ehci_debug->data47);
277 pids = readl(&ehci_debug->pids);
280 ctrl = readl(
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/linux-master/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net_ctrl.c37 caps->crypto_ops = readl(data);
53 hdr = readl(data);
59 u32 hdr = readl(data);
99 caps->me_freq_mhz = readl(data);
124 caps->repr_cap = readl(data);
128 caps->mbox_cmsg_types = readl(data);
/linux-master/arch/arm/mach-sunxi/
H A Dplatsmp.c90 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
94 reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
103 reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
111 reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
174 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
178 reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
/linux-master/drivers/clk/zynq/
H A Dpll.c81 fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
103 reg = readl(clk->pll_ctrl);
129 reg = readl(clk->pll_ctrl);
132 while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
159 reg = readl(clk->pll_ctrl);
214 reg = readl(pll->pll_ctrl);
/linux-master/sound/soc/kirkwood/
H A Dkirkwood-i2s.c69 reg_val = readl(priv->soc_control);
95 reg_val = readl(base + A38X_PLL_CONF_REG1);
121 reg_val = readl(base + A38X_PLL_CONF_REG0);
126 reg_val = readl(base + A38X_PLL_CONF_REG2);
131 reg_val = readl(base + A38X_PLL_CONF_REG1);
175 value = readl(priv->io+KIRKWOOD_I2S_PLAYCTL);
180 value = readl(priv->io+KIRKWOOD_I2S_RECCTL);
210 value = readl(io + KIRKWOOD_DCO_SPCR_STATUS);
269 i2s_value = readl(priv->io+i2s_reg);
354 ctl = readl(pri
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/linux-master/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_ethtool.c132 data = readl(priv->llu_base + MLXBF_GIGE_BF2_LLU_GENERAL_CONFIG);
136 data = readl(priv->llu_base + MLXBF_GIGE_BF3_LLU_GENERAL_CONFIG);
152 data_lo = readl(priv->llu_base + MLXBF_GIGE_TX_PAUSE_CNT_LO);
153 data_hi = readl(priv->llu_base + MLXBF_GIGE_TX_PAUSE_CNT_HI);
156 data_lo = readl(priv->llu_base + MLXBF_GIGE_RX_PAUSE_CNT_LO);
157 data_hi = readl(priv->llu_base + MLXBF_GIGE_RX_PAUSE_CNT_HI);
/linux-master/drivers/clk/mvebu/
H A Darmada-375.c54 tclk_freq_select = ((readl(sar) >> SAR1_A375_TCLK_FREQ_OPT) &
75 cpu_freq_select = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) &
117 u32 opt = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) &
H A Darmada-39x.c49 tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
72 cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
112 if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
H A Darmada-38x.c41 tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) &
58 cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
101 u32 opt = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
H A Darmada-370.c49 tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
69 cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
116 u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
137 return !(readl(sar) & SARL_A370_SSCG_ENABLE);
H A Ddove.c89 u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
108 u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
131 u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
139 u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
/linux-master/drivers/clk/sunxi-ng/
H A Dccu_reset.c23 reg = readl(ccu->base + map->reg);
41 reg = readl(ccu->base + map->reg);
69 return !(map->bit & readl(ccu->base + map->reg));
/linux-master/drivers/clk/visconti/
H A Dpll.c61 val = readl(pll->pll_base + PLL_FRACMODE_REG);
66 rate_table->fracin = readl(pll->pll_base + PLL_FRACIN_REG) & PLL_FRACIN_MASK;
67 rate_table->intin = readl(pll->pll_base + PLL_INTIN_REG) & PLL_INTIN_MASK;
68 rate_table->refdiv = readl(pll->pll_base + PLL_REFDIV_REG) & PLL_REFDIV_MASK;
70 postdiv = readl(pll->pll_base + PLL_POSTDIV_REG);
161 reg = readl(pll->pll_base + PLL_CTRL_REG);
180 reg = readl(pll->pll_base + PLL_CTRL_REG);
186 reg = readl(pll->pll_base + PLL_CTRL_REG);
192 reg = readl(pll->pll_base + PLL_CTRL_REG);
198 reg = readl(pl
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/linux-master/drivers/char/hw_random/
H A Dimx-rngc.c79 ctrl = readl(rngc->base + RNGC_CONTROL);
88 cmd = readl(rngc->base + RNGC_COMMAND);
97 ctrl = readl(rngc->base + RNGC_CONTROL);
110 cmd = readl(rngc->base + RNGC_COMMAND);
129 status = readl(rngc->base + RNGC_STATUS);
137 *(u32 *)data = readl(rngc->base + RNGC_FIFO);
157 status = readl(rngc->base + RNGC_STATUS);
158 rngc->err_reg = readl(rngc->base + RNGC_ERROR);
175 cmd = readl(rngc->base + RNGC_COMMAND);
183 cmd = readl(rng
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/linux-master/drivers/net/ethernet/synopsys/
H A Ddwc-xlgmac-hw.c40 regval = readl(pdata->mac_regs + MAC_RCR);
52 regval = readl(pdata->mac_regs + MAC_RCR);
114 regval = readl(pdata->mac_regs + MAC_VLANTR);
139 regval = readl(pdata->mac_regs + MAC_VLANTR);
151 regval = readl(pdata->mac_regs + MAC_PFR);
157 regval = readl(pdata->mac_regs + MAC_VLANTR);
184 regval = readl(pdata->mac_regs + MAC_PFR);
234 regval = readl(pdata->mac_regs + MAC_VLANHTR);
249 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR),
257 regval = readl(pdat
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/linux-master/arch/sparc/kernel/
H A Debus.c62 val = readl(p->regs + EBDMA_CSR);
77 csr = readl(p->regs + EBDMA_CSR);
136 csr = readl(p->regs + EBDMA_CSR);
142 csr = readl(p->regs + EBDMA_CSR);
163 csr = readl(p->regs + EBDMA_CSR);
186 csr = readl(p->regs + EBDMA_CSR);
231 return readl(p->regs + EBDMA_COUNT);
237 return readl(p->regs + EBDMA_ADDR);
247 orig_csr = csr = readl(p->regs + EBDMA_CSR);
/linux-master/arch/arm/mach-mvebu/
H A Dkirkwood-pm.c22 mem_pm_ctrl = readl(memory_pm_ctrl);

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