Searched refs:readl (Results 151 - 175 of 2405) sorted by relevance

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/linux-master/drivers/phy/marvell/
H A Dphy-pxa-28nm-usb2.c160 reg = readl(base + PHY_28NM_PLL_REG0) &
170 reg = readl(base + PHY_28NM_PLL_REG1);
175 reg = readl(base + PHY_28NM_TX_REG0) & ~PHY_28NM_TX_AMP_MASK;
181 reg = readl(base + PHY_28NM_RX_REG0) & ~PHY_28NM_RX_SQ_THRESH_MASK;
186 reg = readl(base + PHY_28NM_DIG_REG0) &
195 reg = readl(base + PHY_28NM_OTG_REG) | PHY_28NM_OTG_PU_OTG;
239 writel(readl(base + PHY_28NM_CTRL_REG3) |
252 writel(readl(base + PHY_28NM_CTRL_REG3) |
/linux-master/drivers/thermal/broadcom/
H A Dns-thermal.c24 val = readl(pvtmon + PVTMON_CONTROL0);
35 val = readl(pvtmon + PVTMON_STATUS);
/linux-master/drivers/mcb/
H A Dmcb-parse.c25 dtype = readl(p);
54 reg1 = readl(&gdd->reg1);
55 reg2 = readl(&gdd->reg2);
56 offset = readl(&gdd->offset);
57 size = readl(&gdd->size);
124 cb[i].addr = readl(p);
125 cb[i].size = readl(p + 4);
148 reg = readl(*base);
/linux-master/drivers/remoteproc/
H A Dqcom_q6v5_wcss.c161 val = readl(wcss->reg_base + Q6SS_RESET_REG);
166 val = readl(wcss->reg_base + Q6SS_XO_CBCR);
180 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
190 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
199 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
208 val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
212 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
221 val = readl(wcss->reg_base + Q6SS_RESET_REG);
226 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
231 val = readl(wcs
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/linux-master/drivers/bus/
H A Dstm32_rifsc.c75 return !(readl(addr) & SEMCR_MUTEX);
87 FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) != RIF_CID1)
105 FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) == RIF_CID1);
126 sec_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id);
127 cid_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * firewall_id);
210 nb_risup = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF1_MASK;
211 nb_rimu = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF2_MASK;
212 nb_risal = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF3_MASK;
/linux-master/drivers/phy/socionext/
H A Dphy-uniphier-ahci.c79 val = readl(priv->base + CKCTRL0);
89 val = readl(priv->base + CKCTRL1);
96 val = readl(priv->base + RXTXCTRL);
118 val = readl(priv->base + CKCTRL0);
123 val = readl(priv->base + RXTXCTRL);
163 val = readl(priv->base + RXTXCTRL);
168 val = readl(priv->base + CKCTRL0);
184 val = readl(priv->base + RXTXCTRL);
189 val = readl(priv->base + CKCTRL0);
201 val = readl(pri
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/linux-master/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.c25 cfg = readl(dev->regs + GSC_SW_RESET);
38 cfg = readl(dev->regs + GSC_IRQ);
50 cfg = readl(dev->regs + GSC_IRQ);
61 u32 cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
75 u32 cfg = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
111 u32 cfg = readl(dev->regs + GSC_IN_CON);
148 cfg = readl(dev->regs + GSC_IN_CON);
169 cfg = readl(dev->regs + GSC_IN_CON);
222 u32 cfg = readl(dev->regs + GSC_OUT_CON);
268 cfg = readl(de
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/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000_core.c27 u32 value = readl(ioaddr + GMAC_CONTROL);
74 u32 value = readl(ioaddr + GMAC_CONTROL);
83 value = readl(ioaddr + GMAC_CONTROL);
94 reg_space[i] = readl(ioaddr + i * 4);
269 status = readl(ioaddr + GMAC_RGSMIIIS);
301 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
302 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
317 readl(ioaddr + GMAC_PMT);
324 ret = readl(ioaddr + LPI_CTRL_STATUS);
356 value = readl(ioadd
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H A Dstmmac_est.c50 ctrl = readl(est_addr + EST_CONTROL);
86 status = readl(est_addr + EST_STATUS);
102 value = readl(est_addr + EST_SCH_ERR);
119 value = readl(est_addr + EST_FRM_SZ_ERR);
122 value = readl(est_addr + EST_FRM_SZ_CAP);
/linux-master/drivers/net/wireless/quantenna/qtnfmac/
H A Dshm_ipc.c14 const u32 flags = readl(&ipc->shm_region->headroom.hdr.flags);
41 readl(&shm_reg_hdr->flags); /* flush PCIe write */
59 flags = readl(&ipc->shm_region->headroom.hdr.flags);
72 flags = readl(&ipc->shm_region->headroom.hdr.flags);
147 readl(&shm_reg_hdr->flags); /* flush PCIe write */
/linux-master/drivers/irqchip/
H A Dirq-sun4i.c66 val = readl(irq_ic_data->irq_base +
79 val = readl(irq_ic_data->irq_base +
191 hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
193 !(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) &
199 hwirq = readl(irq_ic_data->irq_base +
H A Dirq-realtek-rtl.c46 irr = readl(irr0 + offset) & ~(0xf << shift);
58 value = readl(REG(RTL_ICTL_GIMR));
72 value = readl(REG(RTL_ICTL_GIMR));
111 pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
/linux-master/drivers/clocksource/
H A Dtimer-integrator-ap.c23 return -readl(sched_clk_base + TIMER_VALUE);
72 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
81 u32 ctrl = readl(clkevt_base + TIMER_CTRL) &
91 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
105 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
/linux-master/sound/soc/amd/acp/
H A Dacp-pdm.c39 dmic_ctrl = readl(adata->acp_base + ACP_WOV_MISC_CTRL);
71 dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
84 dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
152 ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));
167 ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));
/linux-master/drivers/rtc/
H A Drtc-aspeed.c28 if (!(readl(rtc->base + RTC_CTRL) & RTC_ENABLE)) {
34 reg2 = readl(rtc->base + RTC_YEAR);
35 reg1 = readl(rtc->base + RTC_TIME);
36 } while (reg2 != readl(rtc->base + RTC_YEAR));
68 ctrl = readl(rtc->base + RTC_CTRL);
H A Drtc-tegra.c64 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
114 readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
115 sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
143 readl(info->base + TEGRA_RTC_REG_SECONDS));
153 sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
164 value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
180 status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
206 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
238 status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
365 readl(inf
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H A Drtc-zynqmp.c92 status = readl(xrtcdev->reg_base + RTC_INT_STS);
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM);
108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
119 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
120 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
135 status = readl(xrtcdev->reg_base + RTC_INT_STS);
173 rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
186 calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD);
263 status = readl(xrtcdev->reg_base + RTC_INT_STS);
334 ret = readl(xrtcde
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/linux-master/drivers/perf/hisilicon/
H A Dhisi_uncore_l3c_pmu.c72 val = readl(l3c_pmu->base + L3C_TRACETAG_CTRL);
78 val = readl(l3c_pmu->base + L3C_PERF_CTRL);
93 val = readl(l3c_pmu->base + L3C_TRACETAG_CTRL);
99 val = readl(l3c_pmu->base + L3C_PERF_CTRL);
123 val = readl(l3c_pmu->base + reg);
141 val = readl(l3c_pmu->base + L3C_DATSRC_CTRL);
159 val = readl(l3c_pmu->base + L3C_DATSRC_CTRL);
175 val = readl(l3c_pmu->base + L3C_PERF_CTRL);
180 val = readl(l3c_pmu->base + L3C_TRACETAG_CTRL);
196 val = readl(l3c_pm
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/linux-master/drivers/gpio/
H A Dgpio-tangier.c90 return !!(readl(gplr) & BIT(shift));
117 value = readl(gpdr);
136 value = readl(gpdr);
150 if (readl(gpdr) & BIT(shift))
168 value = readl(gfbr);
221 value = readl(gimr);
263 value = readl(grer);
270 value = readl(gfer);
281 value = readl(glpr);
289 value = readl(git
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/linux-master/drivers/clk/renesas/
H A Dclk-sh73a0.c83 u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3;
108 if (readl(base + CPG_PLLECR) & BIT(enable_bit)) {
109 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
112 if (readl(enable_reg) & BIT(20))
121 mult = readl(dsi_reg);
H A Dclk-r8a73a4.c69 u32 ckscr = readl(base + CPG_CKSCR);
93 u32 value = readl(base + CPG_PLL0CR);
100 u32 value = readl(base + CPG_PLL1CR);
123 value = readl(base + cr);
159 mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
/linux-master/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.c23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT);
28 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
33 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
76 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
97 flip = readl(dev->regs + FIMC_REG_MSCTRL);
113 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
141 cfg = readl(dev->regs + FIMC_REG_CITAREA);
157 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
187 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
213 u32 cfg = readl(de
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/linux-master/drivers/clk/socfpga/
H A Dclk-pll-s10.c48 reg = readl(socfpgaclk->hw.reg + 0x8);
69 reg = readl(socfpgaclk->hw.reg);
75 reg = readl(socfpgaclk->hw.reg + 0x24);
92 reg = readl(socfpgaclk->hw.reg);
99 reg = readl(socfpgaclk->hw.reg + 0x4);
112 div = ((readl(socfpgaclk->hw.reg) &
125 pll_src = readl(socfpgaclk->hw.reg);
135 pll_src = readl(socfpgaclk->hw.reg);
146 reg = readl(socfpgaclk->hw.reg);
159 reg = readl(socfpgacl
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/linux-master/drivers/net/ethernet/sun/
H A Dsungem.c130 cmd = readl(gp->regs + MIF_FRAME);
168 cmd = readl(gp->regs + MIF_FRAME);
197 (void)readl(gp->regs + GREG_IMASK); /* write posting */
258 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
274 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
277 (readl(gp->regs + PCS_MIISTAT) &
308 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
369 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
381 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
393 if (!(readl(g
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/linux-master/drivers/clk/bcm/
H A Dclk-iproc-pll.c153 u32 val = readl(pll->status_base + ctrl->status.offset);
172 val = readl(base + offset);
181 val = readl(pll->asiu_base + ctrl->asiu.offset);
187 val = readl(pll->control_base + ctrl->aon.offset);
194 val = readl(pll->pwr_base + ctrl->aon.offset);
210 val = readl(pll->control_base + ctrl->aon.offset);
217 val = readl(pll->pwr_base + ctrl->aon.offset);
225 val = readl(pll->asiu_base + ctrl->asiu.offset);
239 val = readl(pll->control_base + reset->offset);
255 val = readl(pl
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Completed in 341 milliseconds

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