Searched refs:read_reg (Results 26 - 50 of 138) sorted by relevance

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/linux-master/drivers/media/dvb-frontends/
H A Dlgdt3305.c151 #define read_reg(state, reg) \ macro
562 gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
563 gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
994 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
995 (read_reg(state, LGDT3305_PT_MSE_2) << 8) |
996 (read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
1001 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
1002 (read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
1003 (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
1009 noise = (read_reg(stat
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H A Dcxd2099.c77 static int read_reg(struct cxd *ci, u8 reg, u8 *val) function
218 read_reg(ci, 0x12, &dummy);
493 read_reg(ci, 0x04, &istat);
506 read_reg(ci, 0x01, &slotstat);
538 read_reg(ci, 0x01, &slotstat);
558 read_reg(ci, 0x0f, &msb);
559 read_reg(ci, 0x10, &lsb);
H A Dstv6111.c337 static int read_reg(struct stv *state, u8 reg, u8 *val) function
350 status = read_reg(state, 9, &regval);
498 read_reg(state, 0x03, &tmp);
503 read_reg(state, 0x08, &tmp);
580 read_reg(state, 2, &reg);
582 read_reg(state, 2, &reg);
/linux-master/drivers/net/can/cc770/
H A Dcc770.h141 priv->read_reg(priv, offsetof(struct cc770_regs, member))
172 u8 (*read_reg)(const struct cc770_priv *priv, int reg); member in struct:cc770_priv
H A Dcc770_isa.c205 priv->read_reg = cc770_isa_mem_read_reg;
212 priv->read_reg = cc770_isa_port_read_reg_indirect;
215 priv->read_reg = cc770_isa_port_read_reg;
300 if (priv->read_reg == cc770_isa_port_read_reg_indirect)
/linux-master/drivers/net/can/sja1000/
H A Dsja1000_isa.c160 priv->read_reg = sja1000_isa_mem_read_reg;
167 priv->read_reg = sja1000_isa_port_read_reg_indirect;
171 priv->read_reg = sja1000_isa_port_read_reg;
238 if (priv->read_reg == sja1000_isa_port_read_reg_indirect)
H A Dems_pci.c202 res = priv->read_reg(priv, SJA1000_CDR);
351 priv->read_reg = ems_pci_v1_read_reg;
357 priv->read_reg = ems_pci_v2_read_reg;
363 priv->read_reg = ems_pci_v3_read_reg;
H A Dplx_pci.c420 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
422 (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) &&
423 (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL))
433 if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL &&
434 priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL &&
435 priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL)
685 priv->read_reg = plx_pci_read_reg;
H A Dsja1000.h160 u8 (*read_reg) (const struct sja1000_priv *priv, int reg); member in struct:sja1000_priv
/linux-master/drivers/net/can/c_can/
H A Dc_can_platform.c148 val = priv->read_reg(priv, index);
149 val |= ((u32)priv->read_reg(priv, index + 1)) << 16;
303 priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
310 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
319 priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
/linux-master/drivers/gpio/
H A Dgpio-brcmstb.c74 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
75 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
107 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
198 iedge_config = bank->gc.read_reg(priv->reg_base +
200 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
202 ilevel = bank->gc.read_reg(priv->reg_base +
501 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
H A Dgpio-grgpio.c150 ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
151 iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
358 priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
/linux-master/drivers/media/pci/ivtv/
H A Divtv-irq.c425 write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x02, IVTV_REG_DMAXFER);
441 write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x01, IVTV_REG_DMAXFER);
544 if (read_reg(IVTV_REG_DMASTATUS) & 0x14) {
546 read_reg(IVTV_REG_DMASTATUS),
548 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
611 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
676 status = read_reg(IVTV_REG_DMASTATUS);
831 unsigned int frame = read_reg(IVTV_REG_DEC_LINE_FIELD) & 1;
928 stat = read_reg(IVTV_REG_IRQSTATUS);
942 (read_reg(IVTV_REG_DEC_LINE_FIEL
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H A Divtv-firmware.c197 write_reg(read_reg(IVTV_REG_SPU) & IVTV_MASK_SPU_ENABLE, IVTV_REG_SPU);
200 write_reg(read_reg(IVTV_REG_VPU) & IVTV_MASK_VPU_ENABLE15, IVTV_REG_VPU);
202 write_reg(read_reg(IVTV_REG_VPU) & IVTV_MASK_VPU_ENABLE16, IVTV_REG_VPU);
/linux-master/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_x550.c337 hw->phy.ops.read_reg = NULL;
537 hw->phy.ops.read_reg = NULL;
1820 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1837 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1856 return hw->phy.ops.read_reg(hw, reg_slice,
1931 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2338 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2346 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2355 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2371 status = hw->phy.ops.read_reg(h
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H A Dixgbe_phy.c242 hw->phy.ops.read_reg(hw,
341 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
346 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
433 status = hw->phy.ops.read_reg(hw,
444 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
1117 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1159 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1222 status = hw->phy.ops.read_reg(h
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H A Dixgbe_82598.c470 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
511 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
512 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
513 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
525 hw->phy.ops.read_reg(hw, 0xC79F,
528 hw->phy.ops.read_reg(hw, 0xC00C,
1178 .read_reg = &ixgbe_read_phy_reg_generic,
/linux-master/drivers/mfd/
H A Dtwl6030-irq.c311 u8 read_reg = 0; local
325 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
328 ret = read_reg & STS_MMC;
/linux-master/drivers/net/ethernet/intel/igc/
H A Digc_mac.c481 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
485 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
501 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
505 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
/linux-master/drivers/iio/imu/bno055/
H A Dbno055_ser_trace.h63 TRACE_EVENT(read_reg,
/linux-master/drivers/mtd/nand/raw/brcmnand/
H A Dbcma_nand.c84 .read_reg = brcmnand_bcma_read_reg,
/linux-master/drivers/net/can/m_can/
H A Dm_can.h65 u32 (*read_reg)(struct m_can_classdev *cdev, int reg); member in struct:m_can_ops
/linux-master/drivers/edac/
H A Daltera_edac.c127 u32 reg, read_reg; local
138 &read_reg);
139 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
150 (read_reg | priv->ue_set_mask));
157 (read_reg | priv->ce_set_mask));
165 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
176 read_reg = READ_ONCE(ptemp[1]);
181 reg, read_reg);
289 u32 read_reg; local
306 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
1089 u32 read_reg; local
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/linux-master/drivers/media/platform/ti/vpe/
H A Dvpdma.c280 static u32 read_reg(struct vpdma_data *vpdma, int offset) function
293 return (read_reg(vpdma, offset) & (mask << shift)) >> shift;
299 u32 val = read_reg(vpdma, offset);
311 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(vpdma, VPDMA_##r))
521 return read_reg(vpdma, VPDMA_LIST_STAT_SYNC) & BIT(list_num + 16);
989 val = read_reg(vpdma, reg_addr);
1003 return read_reg(vpdma, reg_addr);
1012 return read_reg(vpdma, reg_addr);
/linux-master/sound/ppc/
H A Dsnd_ps3.c57 static inline u32 read_reg(unsigned int reg) function
67 u32 newval = read_reg(reg) | or_val;
72 u32 newval = (read_reg(reg) & mask) | or_val;
116 status = read_reg(PS3_AUDIO_KICK(dma_ch)) &
313 port_intr = read_reg(PS3_AUDIO_AX_IS);
400 while ((read_reg(PS3_AUDIO_AO_3WMCTRL) &
630 while (read_reg(PS3_AUDIO_KICK(7)) &

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