/linux-master/drivers/video/fbdev/omap2/omapfb/dss/ |
H A D | hdmi.h | 229 struct dss_pll pll; member in struct:hdmi_pll_data 298 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); 299 void hdmi_pll_compute(struct hdmi_pll_data *pll, 301 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll, 335 struct hdmi_pll_data pll; member in struct:omap_hdmi
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/linux-master/drivers/media/i2c/ccs/ |
H A D | ccs-core.c | 376 struct ccs_pll *pll = &sensor->pll; local 379 rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt_bk.pix_clk_div); 383 rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt_bk.sys_clk_div); 387 rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->vt_fr.pre_pll_clk_div); 391 rval = ccs_write(sensor, PLL_MULTIPLIER, pll->vt_fr.pll_multiplier); 399 DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz, 401 (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 402 sensor->pll.csi2.lanes : 1) << 403 (pll 435 ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll) argument 488 struct ccs_pll *pll = &sensor->pll; local 1063 struct ccs_pll *pll = &sensor->pll; local [all...] |
/linux-master/drivers/clk/microchip/ |
H A D | clk-core.c | 598 static unsigned long spll_calc_mult_div(struct pic32_sys_pll *pll, argument 608 parent_rate /= pll->idiv; 647 struct pic32_sys_pll *pll = clkhw_to_spll(hw); local 652 v = readl(pll->ctrl_reg); 660 pll_in_rate = parent_rate / pll->idiv; 671 struct pic32_sys_pll *pll = clkhw_to_spll(hw); local 673 return spll_calc_mult_div(pll, rate, *parent_rate, NULL, NULL); 679 struct pic32_sys_pll *pll = clkhw_to_spll(hw); local 684 ret = spll_calc_mult_div(pll, rate, parent_rate, &mult, &odiv); 699 spin_lock_irqsave(&pll [all...] |
/linux-master/drivers/clk/ |
H A D | clk-versaclock3.c | 359 const struct vc3_pll_data *pll = vc3->data; local 363 regmap_read(vc3->regmap, pll->int_div_msb_offs, &val); 365 regmap_read(vc3->regmap, pll->int_div_lsb_offs, &val); 368 if (pll->num == VC3_PLL2) { 386 const struct vc3_pll_data *pll = vc3->data; local 389 if (rate < pll->vco_min) 390 rate = pll->vco_min; 391 if (rate > pll->vco_max) 392 rate = pll->vco_max; 396 if (pll 418 const struct vc3_pll_data *pll = vc3->data; local [all...] |
H A D | clk-xgene.c | 64 pr_debug("%s pll %s\n", clk_hw_get_name(hw), 76 u32 pll; local 81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); 90 fvco = parent_rate * (N_DIV_RD(pll) + 4); 97 nref = CLKR_RD(pll) + 1; 98 nout = CLKOD_RD(pll) + 1; 99 nfb = CLKF_RD(pll); 108 nout = SC_OUTDIV2(pll) ? 2 : 3; 109 fvco = parent_rate * SC_N_DIV_RD(pll); 111 pr_debug("%s pll recal [all...] |
/linux-master/drivers/video/fbdev/matrox/ |
H A D | matroxfb_DAC1064.c | 181 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { 589 minfo->features.pll.vco_freq_min = 62000; 590 minfo->features.pll.ref_freq = 14318; 591 minfo->features.pll.feed_div_min = 100; 592 minfo->features.pll.feed_div_max = 127; 593 minfo->features.pll.in_div_min = 1; 594 minfo->features.pll.in_div_max = 31; 595 minfo->features.pll.post_shift_max = 3; 727 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL); 737 matroxfb_g450_setclk(minfo, minfo->values.pll [all...] |
/linux-master/drivers/media/i2c/ |
H A D | ar0521.c | 135 } pll; member in struct:ar0521_dev 247 u32 pll = AR0521_PLL_MAX + 1; local 266 if (new_pll < pll) { 267 pll = new_pll; 273 pll = div64_round(sensor->extclk_freq * (u64)mult, pre); 276 return pll; 334 sensor->pll.vt_pix = bpp / 2; 335 vco = pixel_clock * sensor->pll.vt_pix; 339 sensor->pll.pre = sensor->pll [all...] |
H A D | ccs-pll.h | 3 * drivers/media/i2c/ccs-pll.h 206 * @pll: Given PLL configuration 212 struct ccs_pll *pll);
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/linux-master/drivers/net/wireless/ath/ath9k/ |
H A D | ar9002_phy.c | 309 u32 pll; local 320 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); 321 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); 324 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 326 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 328 return pll;
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/linux-master/sound/soc/codecs/ |
H A D | tscs454.c | 42 struct pll { struct 48 static inline void pll_init(struct pll *pll, int id) argument 50 pll->id = id; 51 mutex_init(&pll->lock); 55 struct pll *pll; member in struct:internal_rate 61 struct pll *pll; member in struct:aif 131 struct pll pll 660 reserve_pll(struct pll *pll) argument 667 free_pll(struct pll *pll) argument [all...] |
/linux-master/drivers/media/dvb-frontends/ |
H A D | dib8000.c | 695 const struct dibx000_bandwidth_config *pll = state->cfg.pll; local 700 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); 702 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | 703 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | 704 (1 << 3) | (pll->pll_range << 1) | 705 (pll->pll_reset << 0); 708 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll 745 dib8000_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio) argument [all...] |
/linux-master/drivers/gpu/drm/hisilicon/hibmc/ |
H A D | hibmc_drm_de.c | 235 struct hibmc_display_panel_pll pll = {0}; local 246 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD); 247 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD); 248 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N); 249 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M); 254 static void set_vclock_hisilicon(struct drm_device *dev, u64 pll) argument 266 writel(pll, priv->mmio + CRT_PLL1_HS); 270 val = pll & ~(CRT_PLL1_HS_POWERON(1));
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/linux-master/drivers/clk/rockchip/ |
H A D | Makefile | 9 clk-rockchip-y += clk-pll.o
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
H A D | nv50.c | 30 #include <subdev/bios/pll.h> 31 #include <subdev/clk/pll.h> 46 nvkm_error(subdev, "failed to retrieve pll data, %d\n", ret); 52 nvkm_error(subdev, "failed pll calculation\n");
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/linux-master/sound/soc/pxa/ |
H A D | pxa-ssp.c | 511 int pll; member in struct:pxa_ssp_clock_mode 517 { .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X }, 518 { .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X }, 519 { .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X }, 520 { .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, 521 { .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, 522 { .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, 523 { .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X },
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/linux-master/drivers/clk/samsung/ |
H A D | Makefile | 6 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
H A D | pllgt215.c | 24 #include "pll.h" 27 #include <subdev/bios/pll.h> 82 nvkm_error(subdev, "unable to find matching pll values\n");
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/linux-master/drivers/gpu/drm/omapdrm/dss/ |
H A D | hdmi.h | 234 struct dss_pll pll; member in struct:hdmi_pll_data 318 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); 320 struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); 357 struct hdmi_pll_data pll; member in struct:omap_hdmi
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/linux-master/arch/m68k/coldfire/ |
H A D | m5272.c | 36 DEFINE_CLK(pll, "pll.0", MCF_CLK); 40 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
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H A D | m54xx.c | 34 DEFINE_CLK(pll, "pll.0", MCF_CLK); 38 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
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/linux-master/drivers/gpu/drm/sprd/ |
H A D | sprd_dsi.h | 89 struct dphy_pll pll; member in struct:dsi_context
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/linux-master/drivers/clk/ingenic/ |
H A D | x1830-cgu.c | 115 .pll = { 138 .pll = { 161 .pll = { 184 .pll = {
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H A D | cgu.h | 20 * @rate_multiplier: the multiplier needed by pll rate calculation 150 * @pll: information valid if type includes CGU_CLK_PLL 177 struct ingenic_cgu_pll_info pll; member in union:ingenic_cgu_clk_info::__anon243
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/linux-master/arch/alpha/include/asm/ |
H A D | core_marvel.h | 269 #define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7) 270 #define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7)
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_ddi.h | 41 struct intel_shared_dpll *pll);
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