Searched refs:nr_channels (Results 26 - 50 of 61) sorted by relevance

123

/linux-master/drivers/edac/
H A Dcell_edac.c152 for (j = 0; j < csrow->nr_channels; j++) {
156 dimm->nr_pages = nr_pages / csrow->nr_channels;
H A Dcpc925_edac.c345 switch (csrow->nr_channels) {
368 for (j = 0; j < csrow->nr_channels; j++) {
370 dimm->nr_pages = nr_pages / csrow->nr_channels;
914 int res = 0, nr_channels; local
946 nr_channels = cpc925_mc_get_channels(vbase) + 1;
952 layers[1].size = nr_channels;
H A Dedac_mc.c115 edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels);
233 csr->nr_channels = tot_channels;
620 for (j = 0; j < csrow->nr_channels; j++)
625 for (j = 0; j < csrow->nr_channels; j++)
765 for (j = 0; j < csrow->nr_channels; j++) {
H A Dedac_mc_sysfs.c167 for (i = 0; i < csrow->nr_channels; i++)
375 if (idx >= csrow->nr_channels)
419 for (chan = 0; chan < csrow->nr_channels; chan++)
701 for (chan = 0; chan < ri->nr_channels; chan++)
828 for (j = 0; j < csrow->nr_channels; j++) {
H A Ddmc520_edac.c462 for (ch = 0; ch < csi->nr_channels; ch++) {
468 dimm->nr_pages = pages_per_rank / csi->nr_channels;
H A Dppc4xx_edac.c958 for (j = 0; j < csi->nr_channels; j++) {
961 dimm->nr_pages = nr_pages / csi->nr_channels;
H A Daspeed_edac.c270 dimm->nr_pages = nr_pages / csrow->nr_channels;
/linux-master/drivers/dma/
H A Dtegra186-gpc-dma.c174 * @nr_channels: Number of channels available in the controller.
181 unsigned int nr_channels; member in struct:tegra_dma_chip_data
1299 .nr_channels = 32,
1307 .nr_channels = 32,
1315 .nr_channels = 32,
1362 struct_size(tdma, channels, cdata->nr_channels),
1399 for (i = 0; i < cdata->nr_channels; i++) {
1490 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1512 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
H A Dimg-mdc-dma.c140 unsigned int nr_channels; member in struct:mdc_dma
919 mdma->nr_channels = (val >> MDC_GLOBAL_CONFIG_A_DMA_CONTEXTS_SHIFT) &
939 &mdma->nr_channels);
966 for (i = 0; i < mdma->nr_channels; i++) {
1007 mdma->nr_channels, mdma->nr_threads);
1049 for (i = 0; i < mdma->nr_channels; i++) {
H A Dstm32-mdma.c254 u32 nr_channels; member in struct:stm32_mdma_device
1597 u32 nr_channels, nr_requests; local
1605 &nr_channels);
1607 nr_channels = STM32_MDMA_MAX_CHANNELS;
1609 nr_channels);
1631 dmadev->nr_channels = nr_channels;
1697 for (i = 0; i < dmadev->nr_channels; i++) {
1784 for (id = 0; id < dmadev->nr_channels; id++) {
H A Dtegra20-apb-dma.c116 * @nr_channels: Number of channels available in the controller.
123 unsigned int nr_channels; member in struct:tegra_dma_chip_data
1369 .nr_channels = 16,
1378 .nr_channels = 32,
1387 .nr_channels = 32,
1396 .nr_channels = 32,
1442 size = struct_size(tdma, channels, cdata->nr_channels);
1482 for (i = 0; i < cdata->nr_channels; i++) {
1568 cdata->nr_channels);
1617 for (i = 0; i < tdma->chip_data->nr_channels;
[all...]
H A Dmxs-dma.c145 unsigned int nr_channels; member in struct:mxs_dma_engine
314 for (i = 0; i != mxs_dma->nr_channels; ++i)
736 if (param.chan_id >= mxs_dma->nr_channels)
754 ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels);
H A Dst_fdma.c721 &fdev->nr_channels);
733 for (i = 0; i < fdev->nr_channels; i++) {
759 fdev->chans = devm_kcalloc(&pdev->dev, fdev->nr_channels,
788 for (i = 0; i < fdev->nr_channels; i++) {
H A Dst_fdma.h144 u32 nr_channels; member in struct:st_fdma_dev
H A Dat_hdmac.c513 * @nr_channels: Number of channels supported by hardware (max 8)
517 unsigned int nr_channels; member in struct:at_dma_platform_data
1874 .nr_channels = 2,
1877 .nr_channels = 8,
1961 struct_size(atdma, chan, plat_dat->nr_channels),
1976 atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
2020 for (i = 0; i < plat_dat->nr_channels; i++) {
2076 plat_dat->nr_channels);
H A Ddmatest.c135 * @nr_channels: number of channels under test
146 unsigned int nr_channels; member in struct:dmatest_info
1070 info->nr_channels++;
1100 info->nr_channels >= params->max_channels)
1163 info->nr_channels = 0;
H A Dowl-dma.c1095 int ret, i, nr_channels, nr_requests; local
1105 ret = of_property_read_u32(np, "dma-channels", &nr_channels);
1118 nr_channels, nr_requests);
1122 od->nr_pchans = nr_channels;
H A Dpch_dma.c804 unsigned int nr_channels; local
808 nr_channels = id->driver_data;
866 for (i = 0; i < nr_channels; i++) {
/linux-master/drivers/dma/dw/
H A Dcore.c1095 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1106 } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1116 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1124 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1149 for (i = 0; i < pdata->nr_channels; i++) {
1162 dwc->priority = pdata->nr_channels - i - 1;
1262 pdata->nr_channels);
/linux-master/arch/sh/drivers/dma/
H A Ddma-sh.c384 .nr_channels = CONFIG_NR_ONCHIP_DMA_CHANNELS,
/linux-master/drivers/dma/dw-axi-dmac/
H A Ddw-axi-dmac.h26 u32 nr_channels; member in struct:dw_axi_dma_hcfg
/linux-master/drivers/xen/events/
H A Devents_fifo.c412 .nr_channels = evtchn_fifo_nr_channels,
H A Devents_2l.c367 .nr_channels = evtchn_2l_max_channels,
/linux-master/include/linux/
H A Dedac.h447 u32 nr_channels; member in struct:csrow_info
/linux-master/drivers/rapidio/devices/
H A Dtsi721_dma.c967 int nr_channels = 0; local
997 nr_channels++;
1000 mport->dma.chancnt = nr_channels;

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