Searched refs:layers (Results 51 - 75 of 81) sorted by relevance

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/linux-master/drivers/edac/
H A Dsynopsys_edac.c1346 struct edac_mc_layer layers[2]; local
1365 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1366 layers[0].size = SYNPS_EDAC_NR_CSROWS;
1367 layers[0].is_virt_csrow = true;
1368 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1369 layers[1].size = SYNPS_EDAC_NR_CHANS;
1370 layers[1].is_virt_csrow = false;
1372 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
H A Digen6_edac.c1167 struct edac_mc_layer layers[2]; local
1182 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1183 layers[0].size = NUM_CHANNELS;
1184 layers[0].is_virt_csrow = false;
1185 layers[1].type = EDAC_MC_LAYER_SLOT;
1186 layers[1].size = NUM_DIMMS;
1187 layers[1].is_virt_csrow = true;
1189 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 0);
H A Di7core_edac.c2134 struct edac_mc_layer layers[2]; local
2138 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2139 layers[0].size = NUM_CHANS;
2140 layers[0].is_virt_csrow = false;
2141 layers[1].type = EDAC_MC_LAYER_SLOT;
2142 layers[1].size = MAX_DIMMS;
2143 layers[1].is_virt_csrow = true;
2144 mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers,
H A Dpnd2_edac.c1309 struct edac_mc_layer layers[2]; local
1319 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1320 layers[0].size = ops->channels;
1321 layers[0].is_virt_csrow = false;
1322 layers[1].type = EDAC_MC_LAYER_SLOT;
1323 layers[1].size = ops->dimms_per_channel;
1324 layers[1].is_virt_csrow = true;
1325 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
H A Daltera_edac.c283 struct edac_mc_layer layers[2]; local
354 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
355 layers[0].size = 1;
356 layers[0].is_virt_csrow = true;
357 layers[1].type = EDAC_MC_LAYER_CHANNEL;
358 layers[1].size = 1;
359 layers[1].is_virt_csrow = false;
360 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
H A Dxgene_edac.c345 struct edac_mc_layer layers[2]; local
380 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
381 layers[0].size = 4;
382 layers[0].is_virt_csrow = true;
383 layers[1].type = EDAC_MC_LAYER_CHANNEL;
384 layers[1].size = 2;
385 layers[1].is_virt_csrow = false;
386 mci = edac_mc_alloc(tmp_ctx.mcu_id, ARRAY_SIZE(layers), layers,
H A Dsb_edac.c3350 struct edac_mc_layer layers[2]; local
3356 layers[0].type = EDAC_MC_LAYER_CHANNEL;
3357 layers[0].size = type == KNIGHTS_LANDING ?
3359 layers[0].is_virt_csrow = false;
3360 layers[1].type = EDAC_MC_LAYER_SLOT;
3361 layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
3362 layers[1].is_virt_csrow = true;
3363 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
H A Damd64_edac.c3938 * For heterogeneous and APU models EDAC CHIP_SELECT and CHANNEL layers
3939 * should be swapped to fit into the layers.
3956 struct edac_mc_layer layers[2]; local
3959 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
3960 layers[0].size = get_layer_size(pvt, 0);
3961 layers[0].is_virt_csrow = true;
3962 layers[1].type = EDAC_MC_LAYER_CHANNEL;
3963 layers[1].size = get_layer_size(pvt, 1);
3964 layers[1].is_virt_csrow = false;
3966 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layer
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/linux-master/drivers/gpu/drm/xlnx/
H A Dzynqmp_kms.c80 struct zynqmp_disp_layer *layer = dpsub->layers[plane->index];
98 struct zynqmp_disp_layer *layer = dpsub->layers[plane->index];
149 struct zynqmp_disp_layer *layer = dpsub->layers[i];
H A Dzynqmp_dp.c1285 * layers are connected.
1291 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_VID];
1293 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX];
1318 if (layer == dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX])
/linux-master/security/landlock/
H A Druleset.h48 /* Makes sure all layers can be checked. */
129 * @num_layers: Number of entries in @layers.
133 * @layers: Stack of layers, from the latest to the newest, implemented
136 struct landlock_layer layers[] __counted_by(num_layers);
211 * @num_layers: Number of layers that are used in this
212 * ruleset. This enables to check that all the layers
220 * A domain saves all layers of merged rulesets in a
222 * last one. These layers are used when merging
226 * layers ar
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/linux-master/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_dev.c75 config_id.max_line_sz = pipe->layers[0]->hsize_in.end;
81 if (pipe->layers[i]->layer_type == KOMEDA_FMT_RICH_LAYER)
H A Dkomeda_plane.c328 err = komeda_plane_add(kms, pipe->layers[j]);
H A Dkomeda_private_obj.c380 err = komeda_layer_obj_add(kms, pipe->layers[j]);
H A Dkomeda_pipeline.h347 * handled by two layers, one layer only handle half of plane image.
410 /** @n_layers: the number of layer on @layers */
412 /** @layers: the pipeline layers */
413 struct komeda_layer *layers[KOMEDA_PIPELINE_MAX_LAYERS]; member in struct:komeda_pipeline
/linux-master/arch/parisc/kernel/
H A Ddrivers.c1042 pr_cont("\t.layers = { 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x }\n",
1043 mod_path.layers[0], mod_path.layers[1], mod_path.layers[2],
1044 mod_path.layers[3], mod_path.layers[4], mod_path.layers[5]);
/linux-master/fs/overlayfs/
H A Dnamei.c51 * that will stop further lookup in lower layers (d->stop=true)
54 * layers (reset d->stop).
285 /* Caught in a trap of overlapping layers */
397 /* Lookup in data-only layers by absolute redirect to layer root */
407 layer = &ofs->layers[ofs->numlayer - ofs->numdatalayer];
432 if (ofs->layers[i].fsid &&
433 ofs->layers[i].fs->bad_uuid)
436 origin = ovl_decode_real_fh(ofs, fh, ofs->layers[i].mnt,
459 .layer = &ofs->layers[i]
881 *layer = &OVL_FS(dentry->d_sb)->layers[
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H A Dexport.c61 * entry /a in the lower layers above layer N and find the indexed dir /a from
63 * will need to verify there are no redirects in lower layers above N. In the
173 * possible when there are redirects in lower layers and non-indexed merge dirs.
463 this = ovl_lookup_real(sb, upper, &ofs->layers[0]);
643 const struct ovl_layer *layer = upper ? &ofs->layers[0] : lowerpath->layer;
H A Dparams.c206 /* count layers, not colons */
308 return invalfc(fc, "regular lower layers cannot follow data layers");
427 * Set "/lower1", "/lower2", and "/lower3" as lower layers and
428 * "/data1" and "/data2" as data lower layers. Any existing lower
429 * layers are replaced.
445 /* drop all existing lower layers */
517 * there are no data layers.
520 pr_err("regular lower layers cannot follow data lower layers");
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/linux-master/drivers/gpu/drm/arm/
H A Dmalidp_hw.h43 u8 layer; /* bitmask of layers supporting it */
115 /* list of supported layers */
117 const struct malidp_layer *layers; member in struct:malidp_hw_regmap
252 /* size of memory used for rotating layers, up to two banks available */
H A Dmalidp_planes.c546 * DP550/650 video layers can accept 3 plane formats only if
964 u8 id = map->layers[i].id;
976 * All the layers except smart layer supports AFBC modifiers.
990 plane->layer = &map->layers[i];
1004 /* Attach the YUV->RGB property only to video layers */
/linux-master/include/uapi/drm/
H A Dpvr_drm.h912 /** @tpc_stride: [IN] Stride between layers in TPC, in pages */
974 /** @layers: [IN] Number of layers. */
975 __u32 layers; member in struct:drm_pvr_ioctl_create_hwrt_dataset_args
/linux-master/drivers/net/ethernet/intel/ice/devlink/
H A Ddevlink.c529 * @layers: value read from flash will be saved here
535 static int ice_get_tx_topo_user_sel(struct ice_pf *pf, uint8_t *layers) argument
551 *layers = ICE_SCHED_5_LAYERS;
553 *layers = ICE_SCHED_9_LAYERS;
564 * @layers: value to be saved in flash
566 * Variable "layers" defines user's preference about number of layers in Tx
572 static int ice_update_tx_topo_user_sel(struct ice_pf *pf, int layers) argument
587 if (layers == ICE_SCHED_5_LAYERS)
643 "Tx scheduling layers hav
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/linux-master/arch/parisc/include/uapi/asm/
H A Dpdc.h380 unsigned int layers[6]; /* device-specific info (ctlr #, unit # ...) */ member in struct:pdc_module_path
/linux-master/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_plane.c989 dc->layers[desc->id] = &plane->layer;
997 const struct atmel_hlcdc_layer_desc *descs = dc->desc->layers;

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