Searched refs:ix (Results 26 - 50 of 91) sorted by relevance

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/linux-master/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Drx_res.h33 u32 mlx5e_rx_res_get_tirn_direct(struct mlx5e_rx_res *res, unsigned int ix);
42 unsigned int ix, bool xsk);
H A Dfs_tt_redirect.c148 int ix = 0; local
178 MLX5_SET_CFG(in, start_flow_index, ix);
179 ix += MLX5E_FS_UDP_GROUP1_SIZE;
180 MLX5_SET_CFG(in, end_flow_index, ix - 1);
188 MLX5_SET_CFG(in, start_flow_index, ix);
189 ix += MLX5E_FS_UDP_GROUP2_SIZE;
190 MLX5_SET_CFG(in, end_flow_index, ix - 1);
430 int ix = 0; local
449 MLX5_SET_CFG(in, start_flow_index, ix);
450 ix
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H A Dqos.c59 int ix; local
61 ix = qid % params->num_channels;
63 c = priv->channels.c[ix];
76 int txq_ix, ix, qid, err = 0; local
112 ix = node_qid % params->num_channels;
114 c = chs->c[ix];
212 int ix; local
216 ix = qid % params->num_channels;
218 c = priv->channels.c[ix];
335 u16 qid = params->num_channels * i + c->ix;
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/linux-master/drivers/net/ethernet/mellanox/mlx5/core/fpga/
H A Dconn.c103 unsigned int ix; local
115 ix = conn->qp.rq.pc & (conn->qp.rq.size - 1);
116 data = mlx5_wq_cyc_get_wqe(&conn->qp.wq.rq, ix);
122 conn->qp.rq.bufs[ix] = buf;
146 unsigned int ix, sgi; local
149 ix = conn->qp.sq.pc & (conn->qp.sq.size - 1);
151 ctrl = mlx5_wq_cyc_get_wqe(&conn->qp.wq.sq, ix);
171 conn->qp.sq.bufs[ix] = buf;
254 int ix, err; local
256 ix
295 int ix; local
607 int ix; local
621 int ix; local
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/linux-master/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/
H A Drx.c19 int mlx5e_xsk_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) argument
21 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, ix);
130 offset = ix * rq->mpwqe.mtts_per_wqe;
160 int mlx5e_xsk_alloc_rx_wqes_batched(struct mlx5e_rq *rq, u16 ix, int wqe_bulk) argument
171 contig = mlx5_wq_cyc_get_size(wq) - ix;
173 alloc = xsk_buff_alloc_batch(rq->xsk_pool, buffs + ix, wqe_bulk);
175 alloc = xsk_buff_alloc_batch(rq->xsk_pool, buffs + ix, contig);
181 int j = mlx5_wq_cyc_ctr2ix(wq, ix + i);
198 int mlx5e_xsk_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, int wqe_bulk) argument
204 int j = mlx5_wq_cyc_ctr2ix(wq, ix
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H A Dsetup.c77 rq->ix = c->ix;
83 rq->stats = &c->priv->channel_stats[c->ix]->xskrq;
85 rq_xdp_ix = c->ix;
/linux-master/drivers/input/misc/
H A Dyealink.c282 int ix, len; local
298 ix = 0;
299 while (size != ix) {
300 len = size - ix;
304 p->offset = cpu_to_be16(ix);
305 memcpy(p->data, &buf[ix], len);
307 ix += len;
317 int i, ix, len; local
319 ix = yld->stat_ix;
327 if (ix >
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/linux-master/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dipsec_fs_roce.c343 int ix = 0; local
351 MLX5_SET_CFG(in, start_flow_index, ix);
352 ix += MLX5_TX_ROCE_GROUP_SIZE;
353 MLX5_SET_CFG(in, end_flow_index, ix - 1);
447 int ix = 0; local
504 MLX5_SET_CFG(in, start_flow_index, ix);
505 ix += 1;
506 MLX5_SET_CFG(in, end_flow_index, ix - 1);
603 int ix = 0; local
633 MLX5_SET_CFG(in, start_flow_index, ix);
714 int ix = 0; local
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H A Dmacsec_fs.c269 int ix = 0; local
291 MLX5_SET_CFG(in, start_flow_index, ix);
292 ix += TX_CRYPTO_TABLE_MKE_GROUP_SIZE;
293 MLX5_SET_CFG(in, end_flow_index, ix - 1);
306 MLX5_SET_CFG(in, start_flow_index, ix);
307 ix += TX_CRYPTO_TABLE_SA_GROUP_SIZE;
308 MLX5_SET_CFG(in, end_flow_index, ix - 1);
317 MLX5_SET_CFG(in, start_flow_index, ix);
318 ix += CRYPTO_TABLE_DEFAULT_RULE_GROUP_SIZE;
319 MLX5_SET_CFG(in, end_flow_index, ix
1057 int ix = 0; local
1272 int ix = 0; local
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/linux-master/include/linux/
H A Ddim.h282 * @ix: Profile index
284 struct dim_cq_moder net_dim_get_rx_moderation(u8 cq_period_mode, int ix);
295 * @ix: Profile index
297 struct dim_cq_moder net_dim_get_tx_moderation(u8 cq_period_mode, int ix);
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/
H A Den_fs.c117 int ix = mlx5e_hash_l2(addr); local
120 hlist_for_each_entry(hn, &hash[ix], hlist)
138 hlist_add_head(&hn->hlist, &hash[ix]);
1015 int ix = 0; local
1036 MLX5_SET_CFG(in, start_flow_index, ix);
1037 ix += MLX5E_L2_GROUP1_SIZE;
1038 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1047 MLX5_SET_CFG(in, start_flow_index, ix);
1048 ix += MLX5E_L2_GROUP2_SIZE;
1049 MLX5_SET_CFG(in, end_flow_index, ix
1132 int ix = 0; local
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H A Dwq.c74 void mlx5_wq_cyc_wqe_dump(struct mlx5_wq_cyc *wq, u16 ix, u8 nstrides) argument
85 wqe = mlx5_wq_cyc_get_wqe(wq, ix);
88 mlx5_wq_cyc_get_size(wq), wq->cur_sz, ix, len);
/linux-master/lib/dim/
H A Dnet_dim.c65 net_dim_get_rx_moderation(u8 cq_period_mode, int ix) argument
67 struct dim_cq_moder cq_moder = rx_profile[cq_period_mode][ix];
85 net_dim_get_tx_moderation(u8 cq_period_mode, int ix) argument
87 struct dim_cq_moder cq_moder = tx_profile[cq_period_mode][ix];
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
H A Dfs_tcp.c184 int ix = 0; local
235 MLX5_SET_CFG(in, start_flow_index, ix);
236 ix += MLX5E_ACCEL_FS_TCP_GROUP1_SIZE;
237 MLX5_SET_CFG(in, end_flow_index, ix - 1);
245 MLX5_SET_CFG(in, start_flow_index, ix);
246 ix += MLX5E_ACCEL_FS_TCP_GROUP2_SIZE;
247 MLX5_SET_CFG(in, end_flow_index, ix - 1);
/linux-master/drivers/infiniband/core/
H A Dcache.c116 /* rwlock protects data_vec[ix]->state and entry pointer.
379 * @ix: GID entry index to delete
383 struct ib_gid_table *table, int ix)
391 ix, table->data_vec[ix]->attr.gid.raw);
394 entry = table->data_vec[ix];
400 table->data_vec[ix] = NULL;
553 int ix; local
566 ix = find_gid(table, gid, attr, default_gid, mask, &empty);
567 if (ix >
382 del_gid(struct ib_device *ib_dev, u32 port, struct ib_gid_table *table, int ix) argument
607 int ix; local
645 int ix; local
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/linux-master/fs/ext4/
H A Dmigrate.c353 struct ext4_extent_idx *ix)
360 block = ext4_idx_pblock(ix);
367 ix = EXT_FIRST_INDEX(eh);
368 for (i = 0; i < le16_to_cpu(eh->eh_entries); i++, ix++) {
369 retval = free_ext_idx(handle, inode, ix);
394 struct ext4_extent_idx *ix; local
400 ix = EXT_FIRST_INDEX(eh);
401 for (i = 0; i < le16_to_cpu(eh->eh_entries); i++, ix++) {
402 retval = free_ext_idx(handle, inode, ix);
352 free_ext_idx(handle_t *handle, struct inode *inode, struct ext4_extent_idx *ix) argument
/linux-master/drivers/s390/char/
H A Dcon3215.c175 int len, count, ix, lines; local
200 ix = req->start;
201 while (lines < RAW3215_MAX_NEWLINE && ix != raw->head) {
202 if (raw->buffer[ix] == 0x15)
204 ix = (ix + 1) & (RAW3215_BUFFER_SIZE - 1);
206 len = ((ix - 1 - req->start) & (RAW3215_BUFFER_SIZE - 1)) + 1;
213 req->delayable = (ix == raw->head) && (len < RAW3215_MIN_WRITE);
215 ix = req->start;
221 ccw->cda = virt_to_dma32(raw->buffer + ix);
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/linux-master/drivers/usb/core/
H A Ddevices.c134 int ix; local
136 for (ix = 0; clas_info[ix].class != -1; ix++)
137 if (clas_info[ix].class == class)
139 return clas_info[ix].class_name;
/linux-master/drivers/iio/chemical/
H A Dsgp30.c418 u16 ix, num_fs; local
458 for (ix = 0; ix < num_fs; ix++) {
459 if (major == supported_versions[ix].major &&
460 minor >= supported_versions[ix].minor)
/linux-master/fs/qnx4/
H A Dinode.c86 int ix; local
100 ix = 0;
102 if ( ix == 0 ) {
115 block = try_extent(&xblk->xblk_xtnts[ix], &offset);
120 if ( ++ix >= xblk->xblk_num_xtnts ) {
122 ix = 0;
/linux-master/drivers/gpu/drm/radeon/
H A Dtrinity_dpm.c541 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; local
548 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
551 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
558 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);
561 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value);
568 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; local
570 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
573 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
580 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; local
582 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
593 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; local
610 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; local
622 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; local
634 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; local
646 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; local
658 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; local
689 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; local
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H A Dr600_dpm.c531 u32 ix = 3 - (3 & index); local
533 WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff);
535 mask = 7 << (3 * ix);
537 tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask);
562 u32 ix = 3 - (3 & index); local
565 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE,
568 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0,
575 u32 ix = 3 - (3 & index); local
577 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
584 u32 ix local
593 u32 ix = 3 - (3 & index); local
603 u32 ix = 3 - (3 & index); local
614 u32 ix = 3 - (3 & index); local
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/linux-master/drivers/gpu/drm/amd/include/
H A Dcgs_common.h134 cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
/linux-master/lib/
H A Dkunit_iov_iter.c570 int ix; local
579 ix = from / PAGE_SIZE;
580 KUNIT_ASSERT_LT(test, ix, npages);
581 p = bpages[ix];
648 int ix; local
657 ix = pr->page + from / PAGE_SIZE;
658 KUNIT_ASSERT_LT(test, ix, npages);
659 p = bpages[ix];
730 int ix; local
733 ix
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/linux-master/drivers/net/ethernet/mscc/
H A Docelot_vcap.c56 u16 ix, int cmd, int sel)
59 VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(ix) |
62 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count)
174 struct vcap_data *data, int ix)
194 col = (ix % num_entries_per_row);
345 static void is2_entry_set(struct ocelot *ocelot, int ix, argument
353 int row = (ix / 2);
364 vcap_data_offset_get(vcap, &data, ix);
669 static void is1_entry_set(struct ocelot *ocelot, int ix, argument
675 int row = ix /
55 vcap_cmd(struct ocelot *ocelot, const struct vcap_props *vcap, u16 ix, int cmd, int sel) argument
173 vcap_data_offset_get(const struct vcap_props *vcap, struct vcap_data *data, int ix) argument
808 es0_entry_set(struct ocelot *ocelot, int ix, struct ocelot_vcap_filter *filter) argument
851 vcap_entry_get(struct ocelot *ocelot, int ix, struct ocelot_vcap_filter *filter) argument
875 vcap_entry_set(struct ocelot *ocelot, int ix, struct ocelot_vcap_filter *filter) argument
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