Lines Matching refs:ix
531 u32 ix = 3 - (3 & index);
533 WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff);
535 mask = 7 << (3 * ix);
537 tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask);
562 u32 ix = 3 - (3 & index);
565 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE,
568 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0,
575 u32 ix = 3 - (3 & index);
577 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
584 u32 ix = 3 - (3 & index);
586 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
593 u32 ix = 3 - (3 & index);
595 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
603 u32 ix = 3 - (3 & index);
608 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK);
614 u32 ix = 3 - (3 & index);
619 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT);