drm/radeon/trinity_dpm.c

541 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
548 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
551 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
558 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);
561 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value);
568 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
570 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
573 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
580 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
582 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
585 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
593 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
595 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
598 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
600 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
603 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
610 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
612 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
615 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
622 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
624 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
627 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
634 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
636 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
639 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
646 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
648 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
651 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
658 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
660 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);
663 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value);
689 	u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
691 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
695 	WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);