Searched refs:idx (Results 426 - 450 of 4003) sorted by relevance

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/linux-master/arch/x86/include/asm/
H A Dbarrier.h36 #define array_index_mask_nospec(idx,sz) ({ \
37 typeof((idx)+(sz)) __idx = (idx); \
/linux-master/drivers/tty/serial/
H A Dserial_base_bus.c225 static int serial_base_add_sparc_console(const char *dev_name, int idx) argument
229 switch (idx) {
240 return serial_base_add_one_prefcon(name, dev_name, idx);
245 static inline int serial_base_add_sparc_console(const char *dev_name, int idx) argument
252 static int serial_base_add_prefcon(const char *name, int idx) argument
261 nmbr_match = kasprintf(GFP_KERNEL, "%i", idx);
265 ret = serial_base_add_one_prefcon(nmbr_match, name, idx);
270 ret = serial_base_add_sparc_console(name, idx);
276 char_match = kasprintf(GFP_KERNEL, "%s%i", name, idx);
280 return serial_base_add_one_prefcon(char_match, name, idx);
329 serial_base_add_isa_preferred_console(const char *name, int idx) argument
[all...]
/linux-master/arch/arm/mm/
H A Dcache-l2x0-pmu.c34 * We ensure that idx 0 -> Counter0, and idx1 -> Counter1.
64 static void l2x0_pmu_counter_config_write(int idx, u32 val) argument
66 writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_CFG - 4 * idx);
69 static u32 l2x0_pmu_counter_read(int idx) argument
71 return readl_relaxed(l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx);
74 static void l2x0_pmu_counter_write(int idx, u32 val) argument
76 writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx);
124 new_count = l2x0_pmu_counter_read(hw->idx);
148 l2x0_pmu_counter_write(hw->idx, 0);
177 static void __l2x0_pmu_event_enable(int idx, u3 argument
203 __l2x0_pmu_event_disable(int idx) argument
232 int idx = l2x0_pmu_find_idx(); local
[all...]
/linux-master/drivers/infiniband/hw/cxgb4/
H A Drestrack.c95 static int fill_swsqe(struct sk_buff *msg, struct t4_sq *sq, u16 idx, argument
98 if (rdma_nl_put_driver_u32(msg, "idx", idx))
307 static int fill_cqe(struct sk_buff *msg, struct t4_cqe *cqe, u16 idx, argument
310 if (rdma_nl_put_driver_u32(msg, qstr, idx))
336 u16 idx; local
338 idx = (cq->cidx > 0) ? cq->cidx - 1 : cq->size - 1;
339 if (fill_cqe(msg, cqes, idx, "hwcq_idx"))
341 idx = cq->cidx;
342 if (fill_cqe(msg, cqes + 1, idx, "hwcq_id
353 u16 idx; local
379 u16 idx; local
[all...]
/linux-master/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.c87 mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask) argument
90 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
96 mt7603_wtbl1_addr(int idx) argument
98 return MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
102 mt7603_wtbl2_addr(int idx) argument
105 return MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE;
109 mt7603_wtbl3_addr(int idx) argument
113 return base + idx * MT_WTBL3_SIZE;
117 mt7603_wtbl4_addr(int idx) argument
121 return base + idx * MT_WTBL4_SIZ
124 mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif, const u8 *mac_addr) argument
170 mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled) argument
181 mt7603_filter_tx(struct mt7603_dev *dev, int mac_idx, int idx, bool abort) argument
241 int idx = sta->wcid.idx; local
272 mt7603_wtbl_clear(struct mt7603_dev *dev, int idx) argument
333 int idx = msta->wcid.idx; local
485 mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast) argument
520 int idx; local
1106 int idx; local
1836 int i, idx; local
[all...]
/linux-master/ipc/
H A Dutil.c204 int idx, next_id = -1; local
229 /* allocate the idx, with a NULL struct kern_ipc_perm */
230 idx = idr_alloc_cyclic(&ids->ipcs_idr, NULL, 0, max_idx,
233 if (idx >= 0) {
235 * idx got allocated successfully.
239 if (idx <= ids->last_idx) {
244 ids->last_idx = idx;
251 idr_replace(&ids->ipcs_idr, new, idx);
255 idx = idr_alloc(&ids->ipcs_idr, new, ipcid_to_idx(next_id),
258 if (idx >
282 int idx, err; local
499 int idx = ipcid_to_idx(ipcp->id); local
630 int idx = ipcid_to_idx(id); local
[all...]
/linux-master/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-qcom-debug.c130 int ret = 0, idx = smmu_domain->cfg.cbndx; local
143 fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
153 sctlr_orig = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_SCTLR);
155 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, sctlr);
156 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);
157 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE);
158 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, sctlr_orig);
268 int idx = smmu_domain->cfg.cbndx; local
296 sctlr_orig = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_SCTLR);
298 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTL
351 int idx = smmu_domain->cfg.cbndx; local
387 int idx = smmu_domain->cfg.cbndx; local
[all...]
/linux-master/drivers/gpu/drm/i915/gt/
H A Dgen8_ppgtt.c148 gen8_pd_range(u64 start, u64 end, int lvl, unsigned int *idx) argument
156 *idx = i915_pde_index(start, shift);
158 return GEN8_PDES - *idx;
160 return i915_pde_index(end, shift) - *idx;
188 gen8_pdp_for_page_index(struct i915_address_space * const vm, const u64 idx) argument
195 return i915_pd_entry(ppgtt->pd, gen8_pd_index(idx, vm->top));
244 unsigned int idx, len; local
248 len = gen8_pd_range(start, end, lvl--, &idx);
249 GTT_TRACE("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d }\n",
251 idx, le
327 unsigned int idx, len; local
414 unsigned int idx, len; local
455 gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, struct i915_page_directory *pdp, struct sgt_dma *iter, u64 idx, unsigned int pat_index, u32 flags) argument
749 u64 idx = vma_res->start >> GEN8_PTE_SHIFT; local
769 u64 idx = offset >> GEN8_PTE_SHIFT; local
790 u64 idx = offset >> GEN8_PTE_SHIFT; local
896 unsigned int idx; local
[all...]
/linux-master/arch/mips/kernel/
H A Dperf_event_mipsxx.c82 u64 (*read_counter)(unsigned int idx);
83 void (*write_counter)(unsigned int idx, u64 val);
184 static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx) argument
187 idx = (idx + 2) & 3;
188 return idx;
191 static u64 mipsxx_pmu_read_counter(unsigned int idx) argument
193 idx = mipsxx_pmu_swizzle_perf_idx(idx);
195 switch (idx) {
214 mipsxx_pmu_read_counter_64(unsigned int idx) argument
234 mipsxx_pmu_write_counter(unsigned int idx, u64 val) argument
254 mipsxx_pmu_write_counter_64(unsigned int idx, u64 val) argument
275 mipsxx_pmu_read_control(unsigned int idx) argument
294 mipsxx_pmu_write_control(unsigned int idx, unsigned int val) argument
348 mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) argument
395 mipsxx_pmu_disable_event(int idx) argument
409 mipspmu_event_set_period(struct perf_event *event, struct hw_perf_event *hwc, int idx) argument
449 mipspmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, int idx) argument
503 int idx; local
539 int idx = hwc->idx; local
723 mipspmu_map_general_event(int idx) argument
782 handle_associated_event(struct cpu_hw_events *cpuc, int idx, struct perf_sample_data *data, struct pt_regs *regs) argument
[all...]
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Datom.c185 uint32_t idx, val = 0xCDCDCDCD, align, arg; local
191 idx = U16(*ptr);
194 DEBUG("REG[0x%04X]", idx);
195 idx += gctx->reg_block;
198 val = gctx->card->reg_read(gctx->card, idx);
219 idx, 0);
223 idx = U8(*ptr);
227 if (idx < ctx->ps_size)
228 val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
230 pr_info("PS index out of range: %i > %i\n", idx, ct
460 val, idx; local
634 int idx = U8((*ptr)++); local
884 int idx = U8(*ptr); local
1595 int idx = CU16(ctx->data_table + offset); local
1615 int idx = CU16(ctx->cmd_table + offset); local
[all...]
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/steering/
H A Ddr_matcher.c414 int idx = 0; local
466 mlx5dr_ste_build_general_purpose(ste_ctx, &sb[idx++],
470 mlx5dr_ste_build_register_0(ste_ctx, &sb[idx++],
474 mlx5dr_ste_build_register_1(ste_ctx, &sb[idx++],
480 mlx5dr_ste_build_src_gvmi_qpn(ste_ctx, &sb[idx++],
486 mlx5dr_ste_build_eth_l2_src_dst(ste_ctx, &sb[idx++],
491 mlx5dr_ste_build_eth_l2_src(ste_ctx, &sb[idx++],
495 mlx5dr_ste_build_eth_l2_dst(ste_ctx, &sb[idx++],
500 mlx5dr_ste_build_eth_l3_ipv6_dst(ste_ctx, &sb[idx++],
504 mlx5dr_ste_build_eth_l3_ipv6_src(ste_ctx, &sb[idx
[all...]
/linux-master/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_util.c184 dev->mt76.global_wcid.idx = 255;
244 int idx = 0; local
248 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT76x02_N_WCIDS);
249 if (idx < 0)
254 msta->wcid.idx = idx;
256 mt76x02_mac_wcid_setup(dev, idx, mvif->idx, sta->addr);
257 mt76x02_mac_wcid_set_drop(dev, idx, false);
272 int idx local
280 mt76x02_vif_init(struct mt76x02_dev *dev, struct ieee80211_vif *vif, unsigned int idx) argument
302 unsigned int idx = 0; local
415 int idx = key->keyidx; local
628 int idx = msta->wcid.idx; local
[all...]
/linux-master/drivers/misc/eeprom/
H A Didt_89hpesx.c263 int idx; local
266 for (idx = 0; idx < seq->bytecnt; idx++) {
269 if (idx == 0)
271 if (idx == seq->bytecnt - 1)
276 seq->data[idx]);
295 int idx; local
298 for (idx = 0; idx < se
328 int idx, evencnt; local
377 int idx, evencnt; local
623 u16 idx; local
686 u16 idx; local
[all...]
/linux-master/include/linux/
H A Dcpufreq.h720 * @idx: the table entry currently being processed
723 #define cpufreq_for_each_entry_idx(pos, table, idx) \
724 for (pos = table, idx = 0; pos->frequency != CPUFREQ_TABLE_END; \
725 pos++, idx++)
745 * @idx: the table entry currently being processed
748 #define cpufreq_for_each_valid_entry_idx(pos, table, idx) \
749 cpufreq_for_each_entry_idx(pos, table, idx) \
760 * @idx: the table entry currently being processed.
764 #define cpufreq_for_each_efficient_entry_idx(pos, table, idx, efficiencies) \
765 cpufreq_for_each_valid_entry_idx(pos, table, idx) \
800 int idx, best = -1; local
822 int idx, best = -1; local
868 int idx, best = -1; local
899 int idx, best = -1; local
936 int idx, best = -1; local
971 int idx, best = -1; local
1013 cpufreq_is_in_limits(struct cpufreq_policy *policy, int idx) argument
1031 int idx; local
[all...]
/linux-master/drivers/net/wireless/silabs/wfx/
H A Dkey.c17 int idx; local
19 idx = ffs(~wdev->key_map) - 1;
20 if (idx < 0 || idx >= MAX_KEY_ENTRIES)
23 wdev->key_map |= BIT(idx);
24 return idx;
27 static void wfx_free_key(struct wfx_dev *wdev, int idx) argument
29 WARN(!(wdev->key_map & BIT(idx)), "inconsistent key allocation");
30 wdev->key_map &= ~BIT(idx);
157 int idx local
[all...]
/linux-master/drivers/gpu/drm/armada/
H A Darmada_plane.c146 unsigned int idx; local
162 idx = 0;
167 armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);
171 armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);
174 armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);
177 armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);
182 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),
184 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),
186 armada_reg_queue_mod(regs, idx, armada_pitch(new_state, 0),
220 armada_reg_queue_mod(regs, idx, cf
233 unsigned int idx = 0; local
[all...]
/linux-master/fs/f2fs/
H A Diostat.c90 int io, idx; local
96 for (idx = 0; idx < MAX_IO_TYPE; idx++) {
98 iostat_lat[idx][io].peak_lat =
99 jiffies_to_msecs(io_lat->peak_lat[idx][io]);
100 iostat_lat[idx][io].cnt = io_lat->bio_cnt[idx][io];
101 iostat_lat[idx][io].avg_lat = iostat_lat[idx][i
[all...]
/linux-master/arch/x86/kernel/apic/
H A Dio_apic.c71 #define for_each_ioapic(idx) \
72 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
73 #define for_each_ioapic_reverse(idx) \
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
75 #define for_each_pin(idx, pin) \
76 for ((pin) = 0; (pin) < ioapics[(idx)]
223 alloc_ioapic_saved_registers(int idx) argument
236 free_ioapic_saved_registers(int idx) argument
263 io_apic_base(int idx) argument
737 irq_active_low(int idx) argument
783 eisa_irq_is_level(int idx, int bus, bool level) argument
796 eisa_irq_is_level(int idx, int bus, bool level) argument
802 irq_is_level(int idx) argument
832 int ioapic, pin, idx; local
1022 mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, unsigned int flags, struct irq_alloc_info *info) argument
1075 pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) argument
1110 int ioapic, pin, idx; local
1210 int idx; local
2228 int idx = find_irq_entry(apic1, pin1, mp_INT); local
2378 ioapic_destroy_irqdomain(int idx) argument
2552 io_apic_unique_id(int idx, u8 id) argument
2559 io_apic_unique_id(int idx, u8 id) argument
2659 io_apic_set_fixmap(enum fixed_addresses idx, phys_addr_t phys) argument
2679 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; local
2771 bad_ioapic_register(int idx) argument
2792 int idx; local
2813 int idx, ioapic, entries; local
[all...]
/linux-master/drivers/misc/
H A Dkgdbts.c174 int idx; member in struct:test_state
369 ts.idx -= 2;
374 ts.idx -= 4;
403 ts.idx++;
408 ts.idx -= go_back;
410 fill_get_buf(ts.tst[ts.idx].get);
434 ts.idx--;
444 ts.idx = -1;
532 ts.idx--;
718 v2printk("get%i: %s\n", ts.idx, get_bu
[all...]
/linux-master/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c595 static void __init mpc512x_clk_setup_mclk(struct mclk_setup_data *entry, size_t idx) argument
604 clks_idx_pub = MPC512x_CLK_PSC0_MCLK + idx;
606 + (idx) * MCLK_MAX_IDX;
607 mccr_reg = &clkregs->psc_ccr[idx];
610 clks_idx_pub = MPC512x_CLK_MSCAN0_MCLK + idx;
612 + (NR_PSCS + idx) * MCLK_MAX_IDX;
613 mccr_reg = &clkregs->mscan_ccr[idx];
622 clks_idx_pub = MPC512x_CLK_OUT0_CLK + idx;
624 + (NR_PSCS + NR_MSCANS + NR_SPDIFS + idx)
626 mccr_reg = &clkregs->out_ccr[idx];
894 size_t idx; /* used as mclk_idx, just to trim line length */ local
1032 int idx; local
[all...]
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_vce.c475 unsigned idx; local
479 idx = radeon_get_ib_value(p, hi);
481 if (idx >= relocs_chunk->length_dw) {
483 idx, relocs_chunk->length_dw);
487 reloc = &p->relocs[(idx / 4)];
564 while (p->idx < p->chunk_ib->length_dw) {
565 uint32_t len = radeon_get_ib_value(p, p->idx);
566 uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);
582 handle = radeon_get_ib_value(p, p->idx + 2);
601 *size = radeon_get_ib_value(p, p->idx
[all...]
/linux-master/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_fdma.c83 int idx = 0; local
86 for (idx = 0; idx < FDMA_RX_DCB_MAX_DBS; ++idx) {
87 struct sparx5_db_hw *db = &dcb->db[idx];
101 int idx = 0; local
104 for (idx = 0; idx < FDMA_TX_DCB_MAX_DBS; ++idx) {
105 struct sparx5_db_hw *db = &dcb->db[idx];
348 int idx, jdx; local
395 int idx, jdx; local
442 int idx; local
[all...]
/linux-master/drivers/gpu/drm/mediatek/
H A Dmtk_disp_ovl.c236 int idx, bool enabled)
238 mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0,
240 DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx));
243 static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, argument
254 reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx);
261 reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx);
295 int mtk_ovl_layer_check(struct device *dev, unsigned int idx, argument
323 void mtk_ovl_layer_on(struct device *dev, unsigned int idx, argument
332 DISP_REG_OVL_RDMA_CTRL(idx));
343 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
235 mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt, int idx, bool enabled) argument
348 mtk_ovl_layer_off(struct device *dev, unsigned int idx, struct cmdq_pkt *cmdq_pkt) argument
397 mtk_ovl_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt) argument
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dconn.c62 nvbios_connEe(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len) argument
66 if (data && idx < cnt)
67 return data + hdr + (idx * *len);
72 nvbios_connEp(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, argument
75 u32 data = nvbios_connEe(bios, idx, ver, len);
H A Dextdev.c63 nvbios_extdev_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) argument
67 if (extdev && idx < cnt)
68 return extdev + idx * *len;
82 nvbios_extdev_parse(struct nvkm_bios *bios, int idx, argument
88 if (!(entry = nvbios_extdev_entry(bios, idx, &ver, &len)))

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