#
597534bd |
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27-Jan-2022 |
Rongwei Liu <rongweil@nvidia.com> |
net/mlx5: DR, Remove 4 members from mlx5dr_ste_htbl to reduce memory Remove chunk_size in struct mlx5dr_icm_chunk and use chunk->size instead. Remove ste_arr/hw_ste_arr/miss_list since they can be accessed from htbl->chunk pointer, no need to keep a copy. This commit reduces 28 bytes from struct mlx5dr_ste_htbl and its size is 32 bytes now. Signed-off-by: Rongwei Liu <rongweil@nvidia.com> Reviewed-by: Shun Hao <shunh@nvidia.com> Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
5c4f9b6e |
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27-Jan-2022 |
Rongwei Liu <rongweil@nvidia.com> |
net/mlx5: DR, Remove icm_addr from mlx5dr_icm_chunk to reduce memory It can be calculated quickly from buddy memory pool by function mlx5dr_icm_pool_get_chunk_icm_addr(). This function is very lightweight and straightforward. Reduce 8 bytes and current size of struct mlx5_dr_icm_chunk is 64 bytes. Signed-off-by: Rongwei Liu <rongweil@nvidia.com> Reviewed-by: Shun Hao <shunh@nvidia.com> Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
6862c787 |
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23-Feb-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for ConnectX-7 steering Add support for a new SW format version that is implemented by ConnectX-7. Except for several differences, the STEv2 is identical to STEv1, so for most callbacks the STEv2 context struct will call STEv1 functions. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
5c422bfa |
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23-Feb-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching on Internet Header Length (IHL) Add support for matching on new field - Internet Header Length (IHL). Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
ffb0753b |
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13-Jan-2022 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Don't allow match on IP w/o matching on full ethertype/ip_version Currently SMFS allows adding rule with matching on src/dst IP w/o matching on full ethertype or ip_version, which is not supported by HW. This patch fixes this issue and adds the check as it is done in DMFS. Fixes: 26d688e33f88 ("net/mlx5: DR, Add Steering entry (STE) utilities") Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
cc2295cd |
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13-Oct-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Improve steering for empty or RX/TX-only matchers Every matcher has RX and TX paths. When a new matcher is created, its RX and TX start/end anchors are connected to the respective RX and TX anchors of the previous and next matchers. This creates a potential performance issue: when a certain rule is added to a matcher, in many cases it is RX or TX only rule, which may create a long chain of RX/TX-only paths w/o the actual rules. This patch aims to handle this issue. RX and TX matchers are now handled separately: matcher connection in the matchers chain is split into two separate lists: RX only and TX only. when a new matcher is created, it is initially created 'detached' - its RX/TX members are not inserted into the table's matcher list. When an actual rule is added, only its appropriate RX or TX nic matchers are then added to the table's nic matchers list and inserted into its place in the chain of matchers. I.e., if the rule that is being added is an RX-only rule, only the RX part of the matcher will be connected to the chain, while TX part of the matcher remains detached and doesn't prolong the TX chain of the matchers. Same goes for rule deletion: when the last RX/TX rule of the nic matcher is destroyed, the nic matcher is removed from its list. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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#
f59464e2 |
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07-Nov-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching on geneve_tlv_option_0_exist field Match on geneve_tlv_option_0_exist field on devices that support STEv1. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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#
09753bab |
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05-Sep-2021 |
Muhammad Sammar <muhammads@nvidia.com> |
net/mlx5: DR, Support matching on tunnel headers 0 and 1 Tunnel headers are generic encapsulation headers, applies for all tunneling protocols identified by the device native parser or by the programmable parser, this support will enable raw matching headers 0 and 1. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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#
8c2b4fee |
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05-Sep-2021 |
Muhammad Sammar <muhammads@nvidia.com> |
net/mlx5: DR, Add misc5 to match_param structs Add misc5 match params to enable matching tunnel headers. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
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#
b5412827 |
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29-Sep-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Warn on failure to destroy objects due to refcount Add WARN_ON_ONCE on refcount checks in SW steering object destructors Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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#
9222f0b2 |
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09-Dec-2020 |
Muhammad Sammar <muhammads@nvidia.com> |
net/mlx5: DR, Add support for dumping steering info Extend mlx5 debugfs support to present Software Steering resources: dr_domain including it's tables, matchers and rules. The interface is read-only. While dump is being presented, new steering rules cannot be inserted/deleted. The steering information is dumped in the CSV form with the following format: <object_type>,<object_ID>, <object_info>,...,<object_info> This data can be read at the following path: /sys/kernel/debug/mlx5/<BDF>/steering/fdb/<domain_handle> Example: # cat /sys/kernel/debug/mlx5/0000:82:00.0/steering/fdb/dmn_000018644 3100,0x55caa4621c50,0xee802,4,65533 3101,0x55caa4621c50,0xe0100008 Changes in V2: - Reduce temp hex buffer size and avoid unnecessary memset - Use bin2hex() instead of DIY loop - Don't check debugfs functions return values Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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#
08fac109 |
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16-Nov-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Rename list field in matcher struct to list_node In dr_types structs, some list fields are list heads, and some are just list nodes that are stored on the other structs' lists. Rename the appropriate list field to reflect this distinction. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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#
c3fb0e28 |
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17-Nov-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Fix lower case macro prefix "mlx5_" to "MLX5_" Macros prefix should be capital letters - fix the prefix in mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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#
84dfac39 |
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13-Dec-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Fix error flow in creating matcher The error code of nic matcher init functions wasn't checked. This patch improves the matcher init function and fix error flow bug: the handling of match parameter is moved into a separate function and error flow is simplified. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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#
455832d4 |
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03-Nov-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Fix check for unsupported fields in match param The existing loop doesn't cast the buffer while scanning it, which results in out-of-bounds read and failure to create the matcher. Fixes: 941f19798a11 ("net/mlx5: DR, Add check for unsupported fields in match param") Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
941f1979 |
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05-Jul-2021 |
Muhammad Sammar <muhammads@nvidia.com> |
net/mlx5: DR, Add check for unsupported fields in match param When a matcher is being built, we "consume" (clear) mask fields one by one, and to verify that we do support all the required fields we check if the whole mask was consumed, else the matching request includes unsupported fields. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
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#
46f2a8ae |
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04-Jul-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Remove HW specific STE type from nic domain Instead of using the HW specific STEv0 type, it is better to use an enum to indicate if this is an RX or TX nic domain. This means that now we will need to convert the nic domain type to the corresponding STE type. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
990467f8 |
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04-Jul-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Skip source port matching on FDB RX domain The FDB RX pipe is connected to the wire and the source port for all incoming packets equals to wire, single uplink port per PF, this means there is no point of matching on the source port in such case. Once we recognize such case, we will optimize the RX steering rule. Note that in such case we clean both source_eswitch_owner_vhca_id and source_port. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
df9dd15a |
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06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching tunnel GTP-U Enable matching on tunnel GTP-U and GTP-U first extension header using dynamic flex parser. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
35ba005d |
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06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Set flex parser for TNL_MPLS dynamically Query the flex_parser id that's intended for TNL_MPLS and use an appropriate flex parser for MPLS over UDP/GRE. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
3442e033 |
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06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for matching on geneve TLV option Enable matching on tunnel geneve TLV option using the flex parser. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
4923938d |
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06-Feb-2021 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Set STEv0 ICMP flex parser dynamically Set the flex parser ID dynamicly for ICMP instead of relying on hardcoded values. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
160e9cb3 |
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24-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Add support for dynamic flex parser Flex parser is a HW parser that can support protocols that are not natively supported by the HCA, such as Geneve (TLV options) and GTP-U. There are 8 such parsers, and each of them can be assigned to parse a specific set of protocols. This patch adds misc4 match params which allows using a correct flex parser that was programmed to the required protocol. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
9f125ced |
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21-Sep-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Allow native protocol support for HW STEv1 Some flex parser protocols are native as part of STEv1. The check for supported protocols was modified to allow this. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
5212f9c6 |
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18-Nov-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Use the new HW specific STE infrastructure Split the STE builders functionality into the common part and device-specific part. All the device-specific part (with 'v0' in the function names) is accessed through the STE context structure. Subsequent patches will have the device-specific logic moved to a separate file. Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
699d531f |
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20-Nov-2020 |
Muhammad Sammar <muhammads@nvidia.com> |
net/mlx5: Check dr mask size against mlx5_match_param size This is to allow passing misc4 match param from userspace when function like ib_flow_matcher_create is called. Signed-off-by: Muhammad Sammar <muhammads@nvidia.com> Reviewed-by: Alex Vesker <valex@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
8a8a1023 |
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31-Aug-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Rename matcher functions to be more HW agnostic Remove flex parser from the matcher function names since the matcher should not be aware of such HW specific details. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
de1facaf |
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31-Aug-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Rename builders HW specific names We will support multiple STE versions. The existing naming is not suitable for newer versions. Removed the HW specific details and renamed with a more general names. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
92b4b885 |
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31-Aug-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Remove unneeded local variable The misc3 variable is used only once and can be dropped. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
e6422d1d |
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31-Aug-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Remove unneeded vlan check from L2 builder When we create a matcher we check that all fields are consumed. There is no need for this specific check. This keeps the STE builder functions simple and clean. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
38a5c59d |
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31-Aug-2020 |
Yevgeny Kliteynik <kliteyn@nvidia.com> |
net/mlx5: DR, Remove unneeded check from source port builder Mask validity for ste builders is checked by mlx5dr_ste_build_pre_check during matcher creation. It already checks the mask value of source_vport, so removing this duplicated check. Also, moving there the check of source_eswitch_owner_vhca_id mask. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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#
22f9d2f4 |
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25-Jul-2020 |
Julia Lawall <Julia.Lawall@inria.fr> |
net/mlx5: drop unnecessary list_empty list_for_each_entry is able to handle an empty list. The only effect of avoiding the loop is not initializing the index variable. Drop list_empty tests in cases where these variables are not used. Note that list_for_each_entry is defined in terms of list_first_entry, which indicates that it should not be used on an empty list. But in list_for_each_entry, the element obtained by list_first_entry is not really accessed, only the address of its list_head field is compared to the address of the list head, so the list_first_entry is safe. The semantic patch that makes this change is as follows (with another variant for the no brace case): (http://coccinelle.lip6.fr/) <smpl> @@ expression x,e; iterator name list_for_each_entry; statement S; identifier i; @@ -if (!(list_empty(x))) { list_for_each_entry(i,x,...) S - } ... when != i ? i = e </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
ffdc8ec0 |
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06-Jul-2020 |
Alex Vesker <valex@mellanox.com> |
net/mlx5: DR, Reduce print level for matcher print There is no need to print on each unsuccessful matcher ip_version combination since it probably will happen when trying to create all the possible combinations. On a real failure we have a print in the calling function. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
ed03a418 |
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20-May-2020 |
Alex Vesker <valex@mellanox.com> |
net/mlx5: DR, Split RX and TX lock for parallel insertion Change the locking flow to support RX and TX locks, splitting the single lock to two will allow inserting rules in parallel for RX and TX parts of the FDB. Locking the dr_domain will be done by locking the RX domain and the TX domain locks, this is mostly used for control operations on the dr_domain. When inserting rules for RX or TX the single nic_doamin RX or TX lock will be used. Splitting the lock is safe since RX and TX domains are logically separated from each other, shared objects such the send-ring and memory pool are protected by locks. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
b7d0db55 |
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12-Jan-2020 |
Erez Shitrit <erezsh@mellanox.com> |
net/mlx5: DR, Improve log messages Few print messages are in debug level where they should be in error, and few messages are missing. Signed-off-by: Erez Shitrit <erezsh@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
f6409299 |
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17-Feb-2020 |
Hamdan Igbaria <hamdani@mellanox.com> |
net/mlx5: DR, Change matcher priority parameter type Change matcher priority parameter type from u16 to u32, this change is needed since sometimes upper levels create a matcher with priority bigger than 2^16. Signed-off-by: Hamdan Igbaria <hamdani@mellanox.com> Reviewed-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
b6d12238 |
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28-Oct-2019 |
Yevgeny Kliteynik <kliteyn@mellanox.com> |
net/mlx5: DR, Add support for Geneve packets SW steering Add support for SW steering matching on Geneve header fields: - VNI - OAM - protocol type - options length Signed-off-by: Yevgeny Kliteynik <kliteyn@mellanox.com> Reviewed-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
6e9e286e |
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28-Oct-2019 |
Yevgeny Kliteynik <kliteyn@mellanox.com> |
net/mlx5: DR, Refactor VXLAN GPE flex parser tunnel code for SW steering Refactor flex parser tunnel code: - Add definition for flex parser tunneling header for VXLAN-GPE - Use macros for VXLAN-GPE SW steering when building STE - Refactor the code to reflect that this is a VXLAN GPE only code and not a general flex parser code. This also significantly simplifies addition of more flex parser protocols, such as Geneve. Signed-off-by: Yevgeny Kliteynik <kliteyn@mellanox.com> Reviewed-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
86bb811b |
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10-Nov-2019 |
Alex Vesker <valex@mellanox.com> |
net/mlx5: DR, Fix matcher builders select check When selecting a matcher ste_builder_arr will always be evaluated as true, instead check if num_of_builders is set for validity. Fixes: 667f264676c7 ("net/mlx5: DR, Support IPv4 and IPv6 mixed matcher") Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
667f2646 |
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27-Oct-2019 |
Alex Vesker <valex@mellanox.com> |
net/mlx5: DR, Support IPv4 and IPv6 mixed matcher Until now SW steering supported matchers that are IPv4 and IPv6. The limitation was mixed matchers in which the outer header IP version was different from the inner header IP version. To support the mixed matcher we create all the possible ste_builder combinations, once we create a rule we select the correct one to be used for rule creation. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
640bdb1f |
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17-Sep-2019 |
Alaa Hleihel <alaa@mellanox.com> |
net/mlx5: DR, Allow matching on vport based on vhca_id In case source_eswitch_owner_vhca_id is given as a match, the source_vport (vhca_id) will be set in case vhca_id_valid. This will allow matching on peer vports, vports that belong to the other pf. Fixes: 26d688e33f88 ("net/mlx5: DR, Add Steering entry (STE) utilities") Signed-off-by: Alaa Hleihel <alaa@mellanox.com> Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
48cbde4b |
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19-Sep-2019 |
Alex Vesker <valex@mellanox.com> |
net/mlx5: DR, Fix getting incorrect prev node in ste_free When we free an STE and the STE is in the middle of collision list, the prev_ste was obtained incorrectly from the list. To avoid such issues list_entry calls replaced with standard list API. Fixes: 26d688e33f88 ("net/mlx5: DR, Add Steering entry (STE) utilities") Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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#
852f660b |
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19-Aug-2019 |
Alex Vesker <valex@mellanox.com> |
net/mlx5: DR, Expose steering matcher functionality Matcher defines which packets fields are matched when a packet arrives. Matcher is a part of a table and can contain one or more rules. Where rule defines specific values of the matcher's mask definition. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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