Searched refs:duty_cycle (Results 26 - 50 of 116) sorted by relevance

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/linux-master/drivers/video/backlight/
H A Dpwm_bl.c80 u64 duty_cycle; local
83 duty_cycle = pb->levels[brightness];
85 duty_cycle = brightness;
87 duty_cycle *= state->period - lth;
88 do_div(duty_cycle, pb->scale);
90 return duty_cycle + lth;
104 state.duty_cycle = compute_duty_cycle(pb, brightness, &state);
113 state.duty_cycle = 0;
636 state.duty_cycle = 0;
652 state.duty_cycle
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/linux-master/drivers/pwm/
H A Dpwm-xilinx.c122 duty_cycles = min_t(u64, state->duty_cycle, U32_MAX * NSEC_PER_SEC);
179 state->duty_cycle = xilinx_timer_get_period(priv, tlr1, tcsr1);
187 if (state->period == state->duty_cycle)
188 state->duty_cycle = 0;
H A Dpwm-microchip-core.c145 duty_steps = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, tmp);
421 state->duty_cycle = state->period;
425 state->duty_cycle = duty_steps * (prescale + 1) * NSEC_PER_SEC;
426 state->duty_cycle = DIV64_U64_ROUND_UP(state->duty_cycle, rate);
H A Dpwm-imx27.c92 unsigned int duty_cycle; member in struct:pwm_imx27_chip
169 val = imx->duty_cycle;
172 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
238 c = clkrate * state->duty_cycle;
273 imx->duty_cycle = duty_cycles;
H A Dpwm-ab8500.c51 * The period is always 1024 q, duty_cycle is between 1q and 1024q.
84 duty_steps = max_t(u64, mul_u64_u64_div_u64(state->duty_cycle,
175 state->duty_cycle = DIV64_U64_ROUND_UP((u64)div * duty_steps, AB8500_PWM_CLKRATE);
H A Dpwm-apple.c57 state->duty_cycle, NSEC_PER_SEC);
91 state->duty_cycle = DIV64_U64_ROUND_UP((u64)on_cycles * NSEC_PER_SEC, fpwm->clkrate);
H A Dpwm-hibvt.c144 state->duty_cycle = div_u64(value * 1000, freq);
162 state->duty_cycle != pwm->state.duty_cycle) {
163 hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);
H A Dpwm-sunplus.c107 if (state->duty_cycle == state->period) {
116 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate,
150 state->duty_cycle = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)duty * NSEC_PER_SEC,
H A Dpwm-bcm-iproc.c92 state->duty_cycle = 0;
108 state->duty_cycle = div64_u64(tmp, rate);
124 * Find period count, duty count and prescale to suit duty_cycle and
139 value = rate * state->duty_cycle;
H A Dpwm-rz-mtu3.c14 * - HW uses one counter and two match components to configure duty_cycle
301 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate);
303 if (state->duty_cycle > state->period)
304 state->duty_cycle = state->period;
352 duty_cycles = mul_u64_u32_div(state->duty_cycle, rz_mtu3_pwm->rate,
H A Dpwm-clps711x.c55 val = mul_u64_u64_div_u64(state->duty_cycle, 0xf, state->period);
H A Dpwm-ntxec.c93 duty = min_t(u64, state->duty_cycle, period);
H A Dpwm-sun4i.c132 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
161 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
183 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
224 div *= state->duty_cycle;
H A Dpwm-sprd.c113 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
190 ret = sprd_pwm_config(spc, pwm, state->duty_cycle,
/linux-master/drivers/hwmon/
H A Dtc654.c127 u8 duty_cycle; /* The DUTY_CYCLE register is a 4-bit read/ member in struct:tc654_data
178 data->duty_cycle = ret & 0x0f;
378 pwm = tc654_pwm_map[data->duty_cycle];
392 data->duty_cycle = 0;
395 data->duty_cycle = val - 1;
403 data->duty_cycle);
463 * State 1 = 30% PWM | duty_cycle = 0
464 * State 2 = ~35% PWM | duty_cycle = 1
466 * State 15 = ~95% PWM | duty_cycle = 14
467 * State 16 = 100% PWM | duty_cycle
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/linux-master/drivers/media/rc/
H A Dir-spi.c99 static int ir_spi_set_duty_cycle(struct rc_dev *dev, u32 duty_cycle) argument
102 int bits = (duty_cycle * 15) / 100;
H A Dserial_ir.c136 unsigned int duty_cycle; member in struct:serial_ir
186 if (serial_ir.duty_cycle > 50)
226 pulse = DIV_ROUND_CLOSEST(serial_ir.duty_cycle * (NSEC_PER_SEC / 100),
228 space = DIV_ROUND_CLOSEST((100 - serial_ir.duty_cycle) *
568 serial_ir.duty_cycle = 50;
673 serial_ir.duty_cycle = cycle;
H A Dene_ir.c319 int carrier, duty_cycle; local
335 duty_cycle = (hperiod * 100) / period;
337 carrier, duty_cycle);
342 .duty_cycle = duty_cycle
901 static int ene_set_tx_duty_cycle(struct rc_dev *rdev, u32 duty_cycle) argument
904 dbg("TX: setting duty cycle to %d%%", duty_cycle);
905 dev->tx_duty_cycle = duty_cycle;
/linux-master/drivers/leds/
H A Dleds-cpcap.c73 static u16 cpcap_led_val(u8 current_limit, u8 duty_cycle) argument
76 duty_cycle &= 0x0f; /* 4 bit */
78 return current_limit << 4 | duty_cycle;
H A Dleds-pwm.c55 led_dat->pwmstate.duty_cycle = duty;
108 brightness *= led_data->pwmstate.duty_cycle;
/linux-master/drivers/media/i2c/cx25840/
H A Dcx25840-ir.c439 unsigned int duty_cycle)
442 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
769 p->duty_cycle = 50;
770 o->duty_cycle = p->duty_cycle;
955 p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle);
956 o->duty_cycle = p->duty_cycle;
1181 .duty_cycle
438 cduty_tx_s_duty_cycle(struct i2c_client *c, unsigned int duty_cycle) argument
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/linux-master/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a.h92 u8 duty_cycle; member in struct:rtw8852a_bb_pmac_info
/linux-master/drivers/regulator/
H A Dpwm-regulator.c162 pstate.duty_cycle = pstate.period;
164 pstate.duty_cycle = 0;
343 pstate.duty_cycle = pstate.period;
345 pstate.duty_cycle = 0;
/linux-master/drivers/media/pci/cx23885/
H A Dcx23888-ir.c459 unsigned int duty_cycle)
462 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
748 o->duty_cycle = p->duty_cycle = 50;
875 p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle);
876 o->duty_cycle = p->duty_cycle;
1133 .duty_cycle = 25, /* 25 % - RC-5 carrier */
458 cduty_tx_s_duty_cycle(struct cx23885_dev *dev, unsigned int duty_cycle) argument
/linux-master/include/media/
H A Drc-core.h211 int (*s_tx_duty_cycle)(struct rc_dev *dev, u32 duty_cycle);
298 u8 duty_cycle; member in struct:ir_raw_event

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