Searched refs:div (Results 226 - 250 of 813) sorted by relevance

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/linux-master/drivers/media/tuners/
H A Dtuner-simple.c441 u16 div, u8 config, u8 cb)
477 buffer[0] = (div>>8) & 0x7f;
478 buffer[1] = div & 0xff;
548 u16 div; local
586 div = params->frequency + IFPCoff + offset;
588 tuner_dbg("Freq= %d.%02d MHz, V_IF=%d.%02d MHz, Offset=%d.%02d MHz, div=%0d\n",
591 offset / 16, offset % 16 * 100 / 16, div);
596 if (t_params->cb_first_if_lower_freq && div < priv->last_div) {
599 buffer[2] = (div>>8) & 0x7f;
600 buffer[3] = div
440 simple_post_tune(struct dvb_frontend *fe, u8 *buffer, u16 div, u8 config, u8 cb) argument
670 u16 div; local
854 u32 div; local
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/linux-master/sound/soc/sh/rcar/
H A Dadg.c78 static u32 rsnd_adg_calculate_brgx(unsigned long div) argument
82 if (!div)
87 if (0 == (div % ratio))
88 return (u32)((i << 8) | ((div / ratio) - 1));
151 int div; local
156 for (div = 2; div <= 98304; div += step) {
157 diff = abs(target_rate - sel_rate[sel] / div);
171 div
573 u32 rate, div; local
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/linux-master/drivers/mfd/
H A Ddb8500-prcmu.c631 * @div: The divider to be applied.
634 * @div should be in the range [1,63] to request a configuration, or 0 to
637 int prcmu_config_clkout(u8 clkout, u8 source, u8 div) argument
648 BUG_ON(div > 63);
651 if (!div && !requests[clkout])
658 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
664 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
672 if (div) {
685 requests[clkout] += (div ? 1 : -1);
871 u32 div; local
1401 u32 div = 1; local
1504 u32 div = 1; local
1531 u32 div; local
1583 u32 div; local
1596 u32 div; local
1706 u32 div; local
1720 u32 div; local
1750 u32 div; local
1876 u32 div; local
1894 u32 div; local
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H A Dmcp-core.c54 * @div: SIB clock divisor
57 * sample rate is SIBCLOCK/div.
59 void mcp_set_telecom_divisor(struct mcp *mcp, unsigned int div) argument
64 mcp->ops->set_telecom_divisor(mcp, div);
72 * @div: SIB clock divisor
76 void mcp_set_audio_divisor(struct mcp *mcp, unsigned int div) argument
81 mcp->ops->set_audio_divisor(mcp, div);
/linux-master/drivers/clk/mvebu/
H A Dcommon.h30 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
H A Dkirkwood.c127 void __iomem *sar, int id, int *mult, int *div)
134 *div = kirkwood_cpu_l2_ratios[opt][1];
142 *div = kirkwood_cpu_ddr_ratios[opt][1];
167 void __iomem *sar, int id, int *mult, int *div)
174 *div = 2;
182 *div = mv88f6180_cpu_ddr_ratios[opt][1];
126 kirkwood_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) argument
166 mv88f6180_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) argument
/linux-master/drivers/media/pci/mantis/
H A Dmantis_vp1033.c81 u32 div; local
86 div = p->frequency / 250;
88 buf[0] = (div >> 8) & 0x7f;
89 buf[1] = div & 0xff;
/linux-master/arch/mips/ath79/
H A Dclock.c71 unsigned int mult, unsigned int div)
76 clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
101 u32 div; local
107 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
108 freq = div * ref_rate;
110 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
111 cpu_rate = freq / div;
113 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
114 ddr_rate = freq / div;
116 div
70 ath79_set_ff_clk(int type, const char *parent, unsigned int mult, unsigned int div) argument
126 u32 mult, div, ddr_div, ahb_div; local
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/linux-master/include/linux/mfd/
H A Ducb1x00.h230 * @div: SIB clock divisor
232 static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div) argument
234 mcp_set_audio_divisor(ucb->mcp, div);
240 * @div: SIB clock divisor
242 static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div) argument
244 mcp_set_telecom_divisor(ucb->mcp, div);
/linux-master/drivers/ufs/host/
H A Dufs-qcom.h232 #define ceil(freq, div) ((freq) % (div) == 0 ? ((freq)/(div)) : ((freq)/(div) + 1))
/linux-master/drivers/media/pci/ttpci/
H A Dbudget.c204 u32 div = (c->frequency + 479500) / 125; local
219 buf[0] = (div >> 8) & 0x7f;
220 buf[1] = div & 0xff;
221 buf[2] = ((div & 0x18000) >> 10) | 0x95;
244 u32 div; local
248 div = (c->frequency + 35937500 + 31250) / 62500;
250 data[0] = (div >> 8) & 0x7f;
251 data[1] = div & 0xff;
252 data[2] = 0x85 | ((div >> 10) & 0x60);
274 u32 div; local
332 u32 div; local
357 u32 div; local
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/linux-master/drivers/clk/meson/
H A DMakefile13 obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
14 obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
/linux-master/drivers/usb/dwc3/
H A Ddwc3-octeon.c251 int div = 0; local
253 while (div < ARRAY_SIZE(clk_div)) {
254 uint64_t rate = octeon_get_io_clock_rate() / clk_div[div];
256 return div;
257 div++;
268 int div; local
293 div = dwc3_octeon_get_divider();
294 if (div < 0) {
296 return div;
300 val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);
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/linux-master/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_dw_hdmi.c25 u16 div; /* PLL dividers */ member in struct:rcar_hdmi_phy_params
72 dw_hdmi_phy_i2c_write(hdmi, params->div, RCAR_HDMI_PHY_PLLDIVCTRL);
/linux-master/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_tmds_clk.c30 u8 *div,
57 if (div && half) {
58 *div = best_m;
149 u8 div; local
152 &div, &half);
162 writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset),
27 sun4i_tmds_calc_divider(unsigned long rate, unsigned long parent_rate, u8 div_offset, u8 *div, bool *half) argument
/linux-master/drivers/clk/sunxi/
H A Dclk-mod0.c25 u8 div, calcm, calcp; local
32 div = DIV_ROUND_UP(req->parent_rate, req->rate);
34 if (div < 16)
36 else if (div / 2 < 16)
38 else if (div / 4 < 16)
43 calcm = DIV_ROUND_UP(div, 1 << calcp);
/linux-master/drivers/clk/
H A Dclk-lan966x.c92 u32 div, val = readl(gck->reg); local
98 div = parent_rate / rate;
100 val |= FIELD_PREP(GCK_PRESCALER, (div - 1));
110 u32 div, val = readl(gck->reg); local
112 div = FIELD_GET(GCK_PRESCALER, val);
114 return parent_rate / (div + 1);
H A Dclk-ast2600.c214 unsigned int mult, div; local
218 mult = div = 1;
225 div = (p + 1);
228 mult, div);
233 unsigned int mult, div; local
238 mult = div = 1;
246 div = (n + 1) * (p + 1);
251 mult = div = 1;
259 div = n + 1;
263 mult, div);
752 u32 val, div, divbits, axi_div, ahb_div; local
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/linux-master/arch/parisc/net/
H A Dbpf_jit_core.c196 u64 hppa_div64(u64 div, u64 divisor) argument
198 div = div64_u64(div, divisor);
199 return div;
202 u64 hppa_div64_rem(u64 div, u64 divisor) argument
205 div64_u64_rem(div, divisor, &rem);
/linux-master/drivers/clk/ti/
H A Dfapll.c74 void __iomem *div; member in struct:fapll_synth
314 if (!synth->div)
345 synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
358 post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
409 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
444 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
466 v = readl_relaxed(synth->div);
470 writel_relaxed(v, synth->div);
486 void __iomem *div,
512 synth->div
484 ti_fapll_synth_setup(struct fapll_data *fd, void __iomem *freq, void __iomem *div, int index, const char *name, const char *parent, struct clk *pll_clk) argument
609 void __iomem *freq, *div; local
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/linux-master/sound/soc/jz4740/
H A Djz4740-i2s.c224 unsigned long div, rate1, rate2, err1, err2; local
226 div = mclk / (64 * rate);
227 if (div == 0)
228 div = 1;
230 rate1 = mclk / (64 * div);
231 rate2 = mclk / (64 * (div + 1));
243 if (div <= i2sdiv_max && err1 <= err2 && err1 < rate/20)
244 return div;
245 if (div < i2sdiv_max && err2 < rate/20)
246 return div
259 int div = 1; local
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/linux-master/drivers/media/pci/bt8xx/
H A Ddvb-bt8xx.c146 u32 div; local
153 div = (((c->frequency + 83333) * 3) / 500000) + IF_FREQUENCYx6;
170 pllbuf[1] = div >> 8;
171 pllbuf[2] = div & 0xff;
272 u32 div; local
275 div = (36000000 + c->frequency + 83333) / 166666;
296 data[0] = (div >> 8) & 0x7f;
297 data[1] = div & 0xff;
298 data[2] = ((div >> 10) & 0x60) | cfg;
304 return (div * 16666
345 u32 div; local
463 u32 div; local
513 u32 div; local
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/linux-master/drivers/net/ethernet/marvell/
H A Dmvmdio.c239 u32 div, freq, cfg; local
251 div = clk_get_rate(mg_core) / (freq + 1) + 1;
254 if (div <= 8)
255 div = MVMDIO_XSMI_CLKDIV_8;
256 else if (div <= 32)
257 div = MVMDIO_XSMI_CLKDIV_32;
258 else if (div <= 64)
259 div = MVMDIO_XSMI_CLKDIV_64;
261 div = MVMDIO_XSMI_CLKDIV_256;
265 cfg |= div;
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/linux-master/sound/soc/sunxi/
H A Dsun8i-codec.c518 u8 div; member in struct:sun8i_codec_clk_div
523 { .div = 1, .val = 0 },
524 { .div = 2, .val = 1 },
525 { .div = 4, .val = 2 },
526 { .div = 6, .val = 3 },
527 { .div = 8, .val = 4 },
528 { .div = 12, .val = 5 },
529 { .div = 16, .val = 6 },
530 { .div = 24, .val = 7 },
531 { .div
543 unsigned int div = sysclk_rate / sample_rate >> lrck_div_order; local
559 unsigned int div = slots * slot_width; local
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/linux-master/drivers/clk/samsung/
H A Dclk-cpu.c161 * div and mask contain the divider value and the register bit mask of the
164 static void exynos_set_safe_div(struct exynos_cpuclk *cpuclk, unsigned long div, argument
172 div0 = (div0 & ~mask) | (div & mask);
281 unsigned long div = 0, div_mask = DIV_MASK; local
302 div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
306 exynos_set_safe_div(cpuclk, div, div_mask);
390 unsigned long div = 0, div_mask = DIV_MASK; local
401 exynos_set_safe_div(cpuclk, div, div_mask);
442 unsigned long divp_rate, div_rate, div; local
460 div
526 unsigned long div = (cfg_data->div0 >> shifts[i]) & 0xf; local
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