Lines Matching refs:div

631  * @div:	The divider to be applied.
634 * @div should be in the range [1,63] to request a configuration, or 0 to
637 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
648 BUG_ON(div > 63);
651 if (!div && !requests[clkout])
658 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
664 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
672 if (div) {
685 requests[clkout] += (div ? 1 : -1);
871 u32 div;
874 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
876 if ((div <= 1) || (div > 15)) {
878 div, __func__);
881 div <<= 1;
883 if (div <= 2)
885 div >>= 1;
888 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1401 u32 div = 1;
1410 div *= d;
1414 div *= d;
1417 div *= 2;
1424 div *= 2;
1426 (void)do_div(rate, div);
1504 u32 div = 1;
1516 div *= 2;
1519 div *= 2;
1523 PLL_RAW) / div;
1531 u32 div;
1533 div = readl(PRCM_DSITVCLK_DIV);
1534 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1535 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1583 u32 div;
1585 div = (src_rate / rate);
1586 if (div == 0)
1588 if (rate < (src_rate / div))
1589 div++;
1590 return div;
1596 u32 div;
1603 div = clock_divider(src_rate, rate);
1606 if (div > 2)
1607 div = 2;
1609 div = 1;
1611 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1618 rounded_rate = (src_rate / min(div, (u32)31));
1706 u32 div;
1712 div = clock_divider(src_rate, rate);
1713 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1720 u32 div;
1725 div = clock_divider(src_rate, rate);
1726 rounded_rate = (src_rate / min(div, (u32)255));
1750 u32 div;
1763 div = clock_divider(src_rate, rate);
1766 if (div > 1)
1774 if (div == 3) {
1780 div = 0;
1783 val |= min(div, (u32)31);
1786 val |= min(div, (u32)31);
1876 u32 div;
1878 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1881 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1882 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1894 u32 div;
1896 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1899 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);