Searched refs:clr (Results 26 - 50 of 230) sorted by relevance

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/linux-master/arch/m68k/ifpsp060/
H A Dos.S94 clr.l %d1 | return success
101 clr.l %d1 | return success
127 clr.l %d1 | return success
134 clr.l %d1 | return success
151 clr.l %d0 | clear whole longword
152 clr.l %d1 | assume success
187 clr.l %d1 | assume success
188 clr.l %d0 | clear whole longword
223 clr.l %d1 | assume success
245 clr
[all...]
/linux-master/drivers/staging/sm750fb/
H A Dsm750_accel.c38 u32 reg, clr; local
45 clr = DE_STRETCH_FORMAT_PATTERN_XY |
53 (read_dpr(accel, DE_STRETCH_FORMAT) & ~clr) | reg);
62 clr = DE_CONTROL_TRANSPARENCY | DE_CONTROL_TRANSPARENCY_MATCH |
66 write_dpr(accel, DE_CONTROL, read_dpr(accel, DE_CONTROL) & ~clr);
/linux-master/arch/m68k/ifpsp060/src/
H A Ditest.S81 clr.l TESTCTR(%a6)
91 clr.l TESTCTR(%a6)
101 clr.l TESTCTR(%a6)
111 clr.l TESTCTR(%a6)
121 clr.l TESTCTR(%a6)
132 clr.l TESTCTR(%a6)
142 clr.l TESTCTR(%a6)
169 clr.l %d1
181 clr.l IREGS+0x8(%a6)
182 clr
[all...]
H A Dilsp.S298 clr.l %d1
313 clr.w %d5
327 clr.l DDNORMAL(%a6) # count of shifts for normalization
328 clr.b DDSECOND(%a6) # clear flag for quotient digits
329 clr.l %d1 # %d1 will hold trial quotient
362 clr.w %d6 # word u3 left
405 clr.l %d2
408 clr.w %d3 # %d3 now ls word of divisor
412 clr.w %d3 # %d3 now ms word of divisor
421 clr
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/core/
H A Dmemory.c49 u32 nr, void (*clr)(struct nvkm_device *, u32, u32),
78 if (clr)
79 clr(device, tags->mn->offset, tags->mn->length);
/linux-master/arch/arm64/kvm/
H A Dpmu.c54 void kvm_clr_pmu_events(u32 clr) argument
61 pmu->events_host &= ~clr;
62 pmu->events_guest &= ~clr;
/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-gpio-defs.h296 uint64_t clr:24; member in struct:cvmx_gpio_tx_clr::cvmx_gpio_tx_clr_s
298 uint64_t clr:24;
305 uint64_t clr:16; member in struct:cvmx_gpio_tx_clr::cvmx_gpio_tx_clr_cn38xx
307 uint64_t clr:16;
314 uint64_t clr:20; member in struct:cvmx_gpio_tx_clr::cvmx_gpio_tx_clr_cn61xx
316 uint64_t clr:20;
H A Dcvmx-led-defs.h193 uint64_t clr:32; member in struct:cvmx_led_udd_dat_clrx::cvmx_led_udd_dat_clrx_s
195 uint64_t clr:32;
/linux-master/drivers/irqchip/
H A Dirq-zevio.c72 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local
101 clr, 0, IRQ_GC_INIT_MASK_CACHE);
H A Dirq-digicolor.c75 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local
106 clr, 0, 0);
H A Dirq-nvic.c75 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local
103 clr, 0, IRQ_GC_INIT_MASK_CACHE);
H A Dirq-orion.c55 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local
70 handle_level_irq, clr, 0,
140 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local
157 handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
/linux-master/arch/alpha/lib/
H A Dclear_user.S63 clr $0 # .. e1 :
95 clr $0 # .. e1 :
/linux-master/drivers/gpio/
H A Dgpio-mmio.c470 * - set/clear pair (named "set" and "clr").
475 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
490 void __iomem *clr,
498 if (set && clr) {
500 gc->reg_clr = clr;
503 } else if (set && !clr) {
582 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
600 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
625 ret = bgpio_setup_io(gc, dat, set, clr, flags);
724 void __iomem *clr; local
487 bgpio_setup_io(struct gpio_chip *gc, void __iomem *dat, void __iomem *set, void __iomem *clr, unsigned long flags) argument
598 bgpio_init(struct gpio_chip *gc, struct device *dev, unsigned long sz, void __iomem *dat, void __iomem *set, void __iomem *clr, void __iomem *dirout, void __iomem *dirin, unsigned long flags) argument
[all...]
/linux-master/drivers/gpu/drm/nouveau/dispnv50/
H A Dwndw.c130 union nv50_wndw_atom_mask clr = { local
131 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask),
133 if (clr.sema ) wndw->func-> sema_clr(wndw);
134 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw);
135 if (clr.xlut ) wndw->func-> xlut_clr(wndw);
136 if (clr.csc ) wndw->func-> csc_clr(wndw);
137 if (clr.image) wndw->func->image_clr(wndw);
413 asyw->clr.xlut = armw->xlut.handle != 0;
428 asyw->clr.csc = armw->csc.valid;
504 asyw->clr
[all...]
H A Dhead.c43 union nv50_head_atom_mask clr = { local
44 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
46 if (clr.crc) nv50_crc_atomic_clr(head);
47 if (clr.olut) head->func->olut_clr(head);
48 if (clr.core) head->func->core_clr(head);
49 if (clr.curs) head->func->curs_clr(head);
418 asyh->clr.core = true;
426 asyh->clr.curs = true;
434 asyh->clr.olut = true;
437 asyh->clr
[all...]
/linux-master/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_crtc.h101 void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set);
/linux-master/arch/x86/boot/compressed/
H A Dident_map_64.c257 pteval_t set, pteval_t clr)
299 if ((set | clr) & _PAGE_ENC) {
306 if (clr)
313 pte = pte_clear_flags(pte, clr);
255 set_clr_page_flags(struct x86_mapping_info *info, unsigned long address, pteval_t set, pteval_t clr) argument
/linux-master/drivers/gpu/drm/xe/
H A Dxe_mmio.h30 u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set);
/linux-master/drivers/pinctrl/
H A Dpinctrl-microchip-sgpio.c188 u32 clr, set; local
192 clr = SGPIO_LUTON_PORT_WIDTH;
197 clr = SGPIO_OCELOT_PORT_WIDTH;
202 clr = SGPIO_SPARX5_PORT_WIDTH;
209 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set);
214 u32 clr, set; local
218 clr = SGPIO_LUTON_CLK_FREQ;
222 clr = SGPIO_OCELOT_CLK_FREQ;
226 clr = SGPIO_SPARX5_CLK_FREQ;
232 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, se
291 u32 clr, set; local
[all...]
/linux-master/arch/arm64/kvm/hyp/include/hyp/
H A Dswitch.h69 #define compute_clr_set(vcpu, reg, clr, set) \
74 clr |= ~hfg & __ ## reg ## _nMASK; \
102 #define compute_undef_clr_set(vcpu, kvm, reg, clr, set) \
106 clr |= hfg & __ ## reg ## _nMASK; \
109 #define update_fgt_traps_cs(hctxt, vcpu, kvm, reg, clr, set) \
120 c |= clr; \
236 u64 clr = 0, set = 0; local
238 compute_clr_set(vcpu, HCRX_EL2, clr, set);
241 hcrx &= ~clr;
/linux-master/arch/sparc/lib/
H A Dbitops.S28 clr %o0
50 clr %o0
72 clr %o0
H A Dcopy_in_user.S97 clr %o0
108 clr %o0
/linux-master/arch/mips/alchemy/devboards/
H A Dbcsr.c73 void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set) argument
80 r &= ~clr;
/linux-master/kernel/irq/
H A Dsettings.h42 irq_settings_clr_and_set(struct irq_desc *desc, u32 clr, u32 set) argument
44 desc->status_use_accessors &= ~(clr & _IRQF_MODIFY_MASK);

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