| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | r9a09g011-cpg.h | 8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
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| /linux-master/drivers/clk/ingenic/ |
| H A D | jz4740-cgu.c | 14 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
106 * Disabling the CPU clock or any parent clocks will hang the
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| H A D | jz4725b-cgu.c | 13 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
91 * Disabling the CPU clock or any parent clocks will hang the
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| /linux-master/drivers/clocksource/ |
| H A D | timer-digicolor.c | 31 #include <linux/sched/clock.h>
173 pr_err("Can't get timer clock\n");
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| /linux-master/drivers/clk/bcm/ |
| H A D | clk-nsp.c | 11 #include <dt-bindings/clock/bcm-nsp.h>
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| /linux-master/drivers/net/can/usb/kvaser_usb/ |
| H A D | kvaser_usb.h | 196 const struct can_clock clock; member in struct:kvaser_usb_dev_cfg
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| /linux-master/include/linux/fsl/ |
| H A D | ptp_qoriq.h | 78 #define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
86 #define COPH (1<<7) /* Generated clock output phase. */
87 #define CIPH (1<<6) /* External oscillator input clock phase */
89 #define BYP (1<<3) /* Bypass drift compensated clock */
91 #define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
128 #define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
145 struct ptp_clock *clock; member in struct:ptp_qoriq
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| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt8167-apmixedsys.c | 8 #include <dt-bindings/clock/mt8167-clk.h>
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| H A D | clk-mt8195-vdo1.c | 9 #include <dt-bindings/clock/mt8195-clk.h>
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| H A D | clk-mt8195-wpe.c | 9 #include <dt-bindings/clock/mt8195-clk.h>
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| H A D | clk-mt6795-pericfg.c | 7 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
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| H A D | clk-mt6795-infracfg.c | 7 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
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| H A D | clk-mt8188-vdo1.c | 11 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
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| H A D | clk-mt2712-mm.c | 13 #include <dt-bindings/clock/mt2712-clk.h>
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| H A D | clk-mt2701-aud.c | 16 #include <dt-bindings/clock/mt2701-clk.h>
136 "could not register clock provider: %s: %d\n",
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| H A D | clk-mt7622-aud.c | 17 #include <dt-bindings/clock/mt7622-clk.h>
121 "could not register clock provider: %s: %d\n",
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| H A D | clk-mt8188-apmixedsys.c | 7 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
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| /linux-master/drivers/gpu/drm/bridge/ |
| H A D | cros-ec-anx7688.c | 81 requiredbw = mode->clock * 8 * 3;
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| /linux-master/drivers/clk/at91/ |
| H A D | at91sam9rl.c | 6 #include <dt-bindings/clock/at91.h>
77 i = of_property_match_string(np, "clock-names", "slow_clk");
83 i = of_property_match_string(np, "clock-names", "main_xtal");
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| /linux-master/drivers/clk/qcom/ |
| H A D | q6sstop-qcs404.c | 15 #include <dt-bindings/clock/qcom,q6sstopcc-qcs404.h>
100 /* TCSR clock */
173 dev_err(&pdev->dev, "failed to acquire iface clock\n");
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| H A D | tcsrcc-sm8550.c | 14 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
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| /linux-master/drivers/net/ethernet/microchip/sparx5/ |
| H A D | sparx5_ptp.c | 48 WARN(1, "Invalid core clock");
70 WARN(1, "Invalid core clock");
85 * because in case of transparent clock the HW will still forward the
579 phc->clock = ptp_clock_register(&phc->info, sparx5->dev);
580 if (IS_ERR(phc->clock))
581 return PTR_ERR(phc->clock);
614 /* Configure the nominal TOD increment per clock cycle */
658 ptp_clock_unregister(sparx5->phc[i].clock);
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| /linux-master/drivers/gpu/drm/bridge/imx/ |
| H A D | imx8qxp-ldb.c | 94 unsigned long di_clk = adj->clock * 1000;
136 unsigned long di_clk = adjusted_mode->clock * 1000;
387 if (mode->clock > 170000)
390 if (mode->clock > 150000 && is_single)
597 "failed to get pixel clock: %d\n", ret);
606 "failed to get bypass clock: %d\n", ret);
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| H A D | imx8qm-ldb.c | 89 unsigned long di_clk = adj->clock * 1000;
136 unsigned long di_clk = adjusted_mode->clock * 1000;
384 if (mode->clock > 300000)
387 if (mode->clock > 150000 && is_single)
458 "failed to get pixel clock: %d\n", ret);
467 "failed to get bypass clock: %d\n", ret);
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| /linux-master/drivers/clk/samsung/ |
| H A D | clk-exynos4412-isp.c | 9 #include <dt-bindings/clock/exynos4.h>
25 /* NOTE: Must be equal to the last clock ID increased by one */
147 { .compatible = "samsung,exynos4412-isp-clock", },
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