/linux-master/drivers/iio/adc/ |
H A D | max77541-adc.c | 100 #define MAX77541_ADC_CHANNEL_V(_channel, _name, _type, _reg) \ 105 .address = _reg, \ 111 #define MAX77541_ADC_CHANNEL_TEMP(_channel, _name, _type, _reg) \ 116 .address = _reg, \
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/linux-master/drivers/iio/accel/ |
H A D | dmard06.c | 39 #define DMARD06_ACCEL_CHANNEL(_axis, _reg) { \ 41 .address = _reg, \ 48 #define DMARD06_TEMP_CHANNEL(_reg) { \ 50 .address = _reg, \
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/linux-master/drivers/clk/mediatek/ |
H A D | clk-mt7622-apmixedsys.c | 20 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ 25 .reg = _reg, \ 41 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 44 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
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H A D | clk-mt6795-topckgen.c | 21 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ 22 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \ 23 (_reg + 0x4), (_reg + 0x8), _shift, _width, \ 26 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ 27 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
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H A D | clk-mt8173-topckgen.c | 22 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ 23 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \ 24 (_reg + 0x4), (_reg + 0x8), _shift, _width, \ 27 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ 28 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
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H A D | clk-mt8195-apusys_pll.c | 28 #define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \ 31 .reg = _reg, \
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H A D | clk-mt8183-apmixedsys.c | 54 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 61 .reg = _reg, \ 81 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 86 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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H A D | clk-mt8365-apmixedsys.c | 19 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 25 .reg = _reg, \ 45 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 49 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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H A D | clk-mt8192-apmixedsys.c | 35 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 42 .reg = _reg, \ 63 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 67 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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H A D | clk-mt2712-apmixedsys.c | 21 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 27 .reg = _reg, \ 44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 47 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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H A D | clk-mt8173-apmixedsys.c | 24 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 29 .reg = _reg, \ 44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 47 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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/linux-master/drivers/net/wireless/ath/ |
H A D | hw.c | 24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg)
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/linux-master/drivers/power/supply/ |
H A D | max77650-charger.c | 21 #define MAX77650_CHG_DETAILS_BITS(_reg) \ 22 (((_reg) & MAX77650_CHG_DETAILS_MASK) >> 4) 52 #define MAX77650_CHGIN_DETAILS_BITS(_reg) \ 53 (((_reg) & MAX77650_CHGIN_DETAILS_MASK) >> 2) 60 #define MAX77650_CHARGER_CHG_CHARGING(_reg) \ 61 (((_reg) & MAX77650_CHARGER_CHG_MASK) > 1)
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/linux-master/drivers/net/ethernet/freescale/fs_enet/ |
H A D | mac-fec.c | 61 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v)) 64 #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg) 67 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v)) 70 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) [all...] |
/linux-master/drivers/net/wireless/ath/ath5k/ |
H A D | ath5k.h | 124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 126 (((_val) << _flags##_S) & (_flags)), _reg) 128 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 129 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 130 (_mask)) | (_flags), _reg) 132 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 133 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 135 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flag [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/ |
H A D | ddc_regs.h | 35 .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\ 58 .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ 75 .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\
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H A D | hpd_regs.h | 40 .type ## _reg = REG(DC_GPIO_HPD_## type),\
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/linux-master/drivers/i2c/busses/ |
H A D | i2c-brcmstb.c | 168 #define __bsc_readl(_reg) ioread32be(_reg) 169 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) 171 #define __bsc_readl(_reg) ioread32(_reg) 172 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) 175 #define bsc_readl(_dev, _reg) \ 176 __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg)) [all...] |
/linux-master/include/linux/soc/mediatek/ |
H A D | mtk_wed.h | 280 #define mtk_wed_device_reg_read(_dev, _reg) \ 281 (_dev)->ops->reg_read(_dev, _reg) 282 #define mtk_wed_device_reg_write(_dev, _reg, _val) \ 283 (_dev)->ops->reg_write(_dev, _reg, _val) 316 #define mtk_wed_device_reg_read(_dev, _reg) 0 317 #define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)
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/linux-master/drivers/ufs/host/ |
H A D | ufs-renesas.c | 41 #define PARAM_RESTORE(_reg, _index) \ 42 { .mode = MODE_RESTORE, .reg = _reg, .index = _index } 45 #define PARAM_SAVE(_reg, _mask, _index) \ 46 { .mode = MODE_SAVE, .reg = _reg, .mask = (u32)(_mask), \ 48 #define PARAM_POLL(_reg, _expected, _mask) \ 49 { .mode = MODE_POLL, .reg = _reg, .u.expected = _expected, \ 54 #define PARAM_WRITE(_reg, _val) \ 55 { .mode = MODE_WRITE, .reg = _reg, .u.val = _val }
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/linux-master/sound/soc/codecs/ |
H A D | adau1373.c | 596 #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \ 598 SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \ 599 SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \ 600 SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \ 601 SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \ 602 SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \ 603 SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \ 604 SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \ 605 SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \ 641 #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \ [all...] |
/linux-master/drivers/net/ethernet/mediatek/ |
H A D | mtk_wed_debugfs.c | 28 #define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ } 29 #define DUMP_REG_MASK(_reg, _mask) \ 30 { #_mask, MTK_##_reg, DUMP_TYPE_WED, 0, MTK_##_mask } 37 #define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED) 38 #define DUMP_WED_MASK(_reg, _mask) DUMP_REG_MASK(_reg, _mask) 41 #define DUMP_WDMA(_reg) DUMP_RE [all...] |
/linux-master/sound/soc/mediatek/mt8195/ |
H A D | mt8195-audsys-clk.c | 28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ 32 .reg = _reg, \ 38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ 39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
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/linux-master/sound/soc/mediatek/mt8188/ |
H A D | mt8188-audsys-clk.c | 28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ 32 .reg = _reg, \ 38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ 39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
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/linux-master/drivers/gpu/drm/msm/adreno/ |
H A D | adreno_gpu.h | 565 #define PKT4(_reg, _cnt) \ 567 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) 598 * registers starting at _reg. 606 #define ADRENO_PROTECT_RW(_reg, _len) \ 608 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 615 #define ADRENO_PROTECT_RDONLY(_reg, _len) \ 617 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
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