Searched refs:_reg (Results 101 - 125 of 170) sorted by relevance

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/linux-master/drivers/net/ethernet/micrel/
H A Dks8851_spi.c70 #define MK_OP(_byteen, _reg) \
71 (BYTE_EN(_byteen) | (_reg) << (8 + 2) | (_reg) >> 6)
/linux-master/drivers/clk/baikal-t1/
H A Dccu-pll.c322 #define CCU_PLL_DBGFS_BIT_ATTR(_name, _reg, _mask) \
325 .reg = _reg, \
329 #define CCU_PLL_DBGFS_FLD_ATTR(_name, _reg, _lsb, _mask, _min, _max) \
332 .reg = _reg, \
/linux-master/drivers/clk/mediatek/
H A Dclk-mt6797.c599 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
604 .reg = _reg, \
619 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
622 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
H A Dclk-mt6765.c671 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
676 .reg = _reg, \
695 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
699 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
/linux-master/drivers/iio/adc/
H A Daxp20x_adc.c44 #define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg) \
49 .address = _reg, \
55 #define AXP20X_ADC_CHANNEL_OFFSET(_channel, _name, _type, _reg) \
60 .address = _reg, \
/linux-master/drivers/dma/
H A Dpxa_dma.c145 #define _phy_readl_relaxed(phy, _reg) \
146 readl_relaxed((phy)->base + _reg((phy)->idx))
147 #define phy_readl_relaxed(phy, _reg) \
150 _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \
152 "%s(): readl(%s): 0x%08x\n", __func__, #_reg, \
156 #define phy_writel(phy, val, _reg) \
158 writel((val), (phy)->base + _reg((phy)->idx)); \
161 __func__, (u32)(val), #_reg); \
163 #define phy_writel_relaxed(phy, val, _reg) \
165 writel_relaxed((val), (phy)->base + _reg((ph
[all...]
/linux-master/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7734.c69 #define DIV4(_reg, _bit, _mask, _flags) \
70 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
H A Dclock-sh7724.c150 #define DIV4(_reg, _bit, _mask, _flags) \
151 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
H A Dclock-sh7723.c111 #define DIV4(_reg, _bit, _mask, _flags) \
112 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/linux-master/drivers/irqchip/
H A Dirq-pic32-evic.c118 #define IRQ_REG_MASK(_hwirq, _reg, _mask) \
120 _reg = _hwirq / 32; \
/linux-master/drivers/net/wireless/mediatek/mt7601u/
H A Dmt7601u.h297 #define mt76_rmw_field(_dev, _reg, _field, _val) \
298 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
/linux-master/drivers/clk/at91/
H A Dpmc.h117 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
/linux-master/drivers/regulator/
H A Dmax77650-regulator.c16 #define MAX77650_REGULATOR_EN_CTRL_BITS(_reg) \
17 ((_reg) & MAX77650_REGULATOR_EN_CTRL_MASK)
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_pm_debugfs.c19 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
/linux-master/arch/powerpc/kernel/ptrace/
H A Dptrace.c383 #define CHECK_REG(_pt, _reg) \
384 BUILD_BUG_ON(_pt != (offsetof(struct user_pt_regs, _reg) / \
/linux-master/drivers/soc/sunxi/
H A Dsunxi_sram.c51 #define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \
54 .reg = _reg, \
/linux-master/drivers/iio/imu/bno055/
H A Dbno055_ser_core.c300 const void *_reg, size_t reg_size,
305 const u8 *reg = _reg;
299 bno055_ser_read_reg(void *context, const void *_reg, size_t reg_size, void *val, size_t val_size) argument
/linux-master/drivers/clk/meson/
H A Dg12a-aoclk.c46 #define AXG_AO_GATE(_name, _reg, _bit) \
49 .offset = (_reg), \
/linux-master/drivers/net/wireless/ath/ath9k/
H A Dhw.h79 #define REG_WRITE(_ah, _reg, _val) \
80 (_ah)->reg_ops.write((_ah), (_val), (_reg))
82 #define REG_READ(_ah, _reg) \
83 (_ah)->reg_ops.read((_ah), (_reg))
88 #define REG_RMW(_ah, _reg, _set, _clr) \
89 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
/linux-master/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dtestmode.c26 #define REG_BAND(_list, _reg) \
27 { _list.band[0] = MT_##_reg(0); \
28 _list.band[1] = MT_##_reg(1); }
29 #define REG_BAND_IDX(_list, _reg, _idx) \
30 { _list.band[0] = MT_##_reg(0, _idx); \
31 _list.band[1] = MT_##_reg(1, _idx); }
/linux-master/drivers/clk/
H A Dclk-k210.c49 #define K210_GATE(_reg, _bit) \
50 .gate_reg = (_reg), \
53 #define K210_DIV(_reg, _shift, _width, _type) \
54 .div_reg = (_reg), \
59 #define K210_MUX(_reg, _bit) \
60 .mux_reg = (_reg), \
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.h59 #define CLUSTER(_id, _reg, _sel_reg, _sel_val) \
61 .registers = _reg, \
62 .count = ARRAY_SIZE(_reg), \
133 #define CLUSTER_DBGAHB(_id, _base, _type, _reg) \
135 .registers = _reg, .count = ARRAY_SIZE(_reg) }
/linux-master/drivers/clk/nxp/
H A Dclk-lpc32xx.c1093 #define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable) \
1101 .reg = LPC32XX_CLKPWR_ ## _reg, \
1109 #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \
1119 .reg = LPC32XX_CLKPWR_ ## _reg, \
1130 #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \
1138 .reg = LPC32XX_CLKPWR_ ## _reg, \
1149 #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \
1157 .reg = LPC32XX_CLKPWR_ ## _reg, \
1166 #define LPC32XX_DEFINE_CLK(_idx, _reg, _e, _em, _d, _dm, _b, _bm, _ops) \
1174 .reg = LPC32XX_CLKPWR_ ## _reg, \
[all...]
/linux-master/drivers/media/dvb-frontends/
H A Dstv0910.c205 #define SET_FIELD(_reg, _val) \
206 write_field(state, state->nr ? FSTV0910_P2_##_reg : \
207 FSTV0910_P1_##_reg, _val)
209 #define SET_REG(_reg, _val) \
210 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
211 RSTV0910_P1_##_reg, _val)
213 #define GET_REG(_reg, _val) \
214 read_reg(state, state->nr ? RSTV0910_P2_##_reg : \
215 RSTV0910_P1_##_reg, _val)
/linux-master/drivers/gpu/drm/vc4/
H A Dvc4_hdmi_regs.h149 #define _VC4_REG(_base, _reg, _offset) \
150 [_reg] = { \
151 .name = #_reg, \

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