Searched refs:REG (Results 51 - 75 of 296) sorted by relevance

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/linux-master/drivers/watchdog/
H A Dit8712f_wdt.c56 #define REG 0x2e /* The register to read/write */ macro
94 outb(reg, REG);
100 outb(reg, REG);
107 outb(reg++, REG);
109 outb(reg, REG);
116 outb(LDN, REG);
123 * Try to reserve REG and REG + 1 for exclusive access.
125 if (!request_muxed_region(REG, 2, NAME))
128 outb(0x87, REG);
[all...]
H A Dit87_wdt.c39 #define REG 0x2e macro
110 * Try to reserve REG and REG + 1 for exclusive access.
112 if (!request_muxed_region(REG, 2, WATCHDOG_NAME))
115 outb(0x87, REG);
116 outb(0x01, REG);
117 outb(0x55, REG);
118 outb(0x55, REG);
124 outb(0x02, REG);
126 release_region(REG,
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/linux-master/arch/sparc/kernel/
H A Dpsycho_common.h15 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
18 ((unsigned long)(REG)))
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/
H A Dgeneric_regs.h32 .type ## _reg = REG(DC_GPIO_GENERIC_## type),\
46 .mux = REG(DC_GENERIC ## id),\
/linux-master/tools/testing/selftests/ftrace/test.d/dynevent/
H A Dfprobe_syntax_errors.tc12 REG=%ax ;;
14 REG=%x0 ;;
16 REG=%r0 ;;
41 check_error 'f vfs_read ^'$REG # BAD_VAR
/linux-master/arch/loongarch/kernel/
H A Dhw_breakpoint.c36 #define READ_WB_REG_CASE(OFF, N, REG, T, VAL) \
38 LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL); \
41 #define WRITE_WB_REG_CASE(OFF, N, REG, T, VAL) \
43 LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL); \
46 #define GEN_READ_WB_REG_CASES(OFF, REG, T, VAL) \
47 READ_WB_REG_CASE(OFF, 0, REG, T, VAL); \
48 READ_WB_REG_CASE(OFF, 1, REG, T, VAL); \
49 READ_WB_REG_CASE(OFF, 2, REG, T, VAL); \
50 READ_WB_REG_CASE(OFF, 3, REG, T, VAL); \
51 READ_WB_REG_CASE(OFF, 4, REG,
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn303/
H A Ddcn303_hwseq.c38 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/i2c/
H A Dtda998x_drv.c104 #define REG(page, addr) (((page) << 8) | (addr)) macro
112 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
113 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
120 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
121 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
124 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
125 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
126 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
130 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
134 #define REG_INT_FLAGS_0 REG(
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/linux-master/drivers/gpu/drm/tilcdc/
H A Dtilcdc_drv.c394 #define REG(rev, save, reg) { #reg, rev, save, reg } macro
396 REG(1, false, LCDC_PID_REG),
397 REG(1, true, LCDC_CTRL_REG),
398 REG(1, false, LCDC_STAT_REG),
399 REG(1, true, LCDC_RASTER_CTRL_REG),
400 REG(1, true, LCDC_RASTER_TIMING_0_REG),
401 REG(1, true, LCDC_RASTER_TIMING_1_REG),
402 REG(1, true, LCDC_RASTER_TIMING_2_REG),
403 REG(1, true, LCDC_DMA_CTRL_REG),
404 REG(
415 #undef REG macro
[all...]
/linux-master/drivers/gpio/
H A Dgpio-it87.c37 #define REG 0x2e macro
80 * Try to reserve REG and REG + 1 for exclusive access.
82 if (!request_muxed_region(REG, 2, KBUILD_MODNAME))
85 outb(0x87, REG);
86 outb(0x01, REG);
87 outb(0x55, REG);
88 outb(0x55, REG);
94 outb(0x02, REG);
96 release_region(REG,
[all...]
/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h43 #define REG(reg) (REGS)->offset.reg macro
51 #define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
54 ((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
59 dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
86 dmub_reg_update(CTX, REG(reg_name), n, __VA_ARGS__)
113 dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c33 #define REG(reg)\ macro
120 if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
140 if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
148 if (REG(DCFEV_CLOCK_CONTROL))
200 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.c37 #define REG(reg)\ macro
52 if (REG(DOMAIN1_PG_CONFIG) == 0)
109 if (REG(DOMAIN0_PG_CONFIG) == 0)
168 if (REG(DOMAIN16_PG_CONFIG) == 0)
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dwb.c28 #define REG(reg)\ macro
H A Ddcn35_mmhubbub.c30 #define REG(reg) \ macro
H A Ddcn35_opp.c30 #define REG(reg) ((const struct dcn35_opp_registers *)(oppn20->regs))->reg macro
/linux-master/drivers/gpu/drm/amd/display/dc/dsc/dcn35/
H A Ddcn35_dsc.c34 #define REG(reg)\ macro
/linux-master/arch/arm64/include/asm/
H A Dhw_breakpoint.h98 #define AARCH64_DBG_READ(N, REG, VAL) do {\
99 VAL = read_sysreg(dbg##REG##N##_el1);\
102 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\
103 write_sysreg(VAL, dbg##REG##N##_el1);\
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c33 #define REG(reg)\ macro
55 if (REG(MUX[opp_id]))
71 if (mpcc_id < MAX_OPP && REG(MUX[mpcc_id]))
226 gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]);
227 gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]);
228 gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);
229 gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
230 gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
231 gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
232 gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_
[all...]
/linux-master/drivers/block/
H A Dswim.c41 #define REG(x) unsigned char x, x ## _pad[0x200 - 1]; macro
44 REG(write_data)
45 REG(write_mark)
46 REG(write_CRC)
47 REG(write_parameter)
48 REG(write_phase)
49 REG(write_setup)
50 REG(write_mode0)
51 REG(write_mode1)
53 REG(read_dat
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/linux-master/drivers/scsi/
H A Dsun3x_esp.c43 #define dma_read32(REG) \
44 readl(esp->dma_regs + (REG))
45 #define dma_write32(VAL, REG) \
46 writel((VAL), esp->dma_regs + (REG))
48 #define dma_read32(REG) \
49 *(volatile u32 *)(esp->dma_regs + (REG))
50 #define dma_write32(VAL, REG) \
51 do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_hubbub.c29 #define REG(reg)\ macro
40 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c36 #define REG(reg)\ macro
195 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
196 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
198 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
199 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
256 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
257 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
264 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
265 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
346 icsc_regs.csc_c11_c12 = REG(CM_ICSC_C11_C1
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.c31 #define REG(reg)\ macro
41 #define REG(reg)\ macro
415 if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
497 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A))
499 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
508 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B))
510 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
519 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C))
521 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
530 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_
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/linux-master/drivers/ptp/
H A Dptp_clockmatrix.h65 #define IDTCM_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))

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